library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity TB_PWM_MODULE_CLK_EN is
end TB_PWM_MODULE_CLK_EN;

architecture tb of TB_PWM_MODULE_CLK_EN is

component PWM_MODULE_CLK_EN is
    generic
	(
		P                              : integer
	);
    port
	(
		CLK_100MHZ_PIN                 : in    std_logic;    
		ARESETN_PIN                    : in    std_logic;
		CLK_EN_OUT                     : out   std_logic
    ); 
end component;

signal CLK_100MHZ_PIN                  : std_logic := '1';
signal ARESETN_PIN                     : std_logic := '1';
signal CLK_EN_OUT                      : std_logic := '0';

begin

CLK_100MHZ_PIN                         <= not CLK_100MHZ_PIN after 5 ns;

process begin
	wait for 500 ns;
	ARESETN_PIN                        <= '0';
	wait for 500 ns;
	ARESETN_PIN                        <= '1';
	wait;
end process;

inst_PWM_MODULE_CLK_EN : PWM_MODULE_CLK_EN
    generic map
	(
		P                              => 20
	)
    port map
	(
		CLK_100MHZ_PIN                 => CLK_100MHZ_PIN,
		ARESETN_PIN                    => ARESETN_PIN,
		CLK_EN_OUT                     => CLK_EN_OUT
    ); 

end;