library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity filter is
	generic
	(  -- Q = 14
		b0 : signed(15 downto 0) := to_signed(16,16); 		-- b0 = 0,00094469  -> b0*2^14 = 16
		b1 : signed(15 downto 0) := to_signed(31,16); 		-- b1 = 0,00188940  -> b1*2^14 = 31
		b2 : signed(15 downto 0) := to_signed(62,16); 		-- b2 = b0
		a1 : signed(15 downto 0) := to_signed(-31313,16);  -- a1 = -1,91120934 -> a1*2^14 = -31313
		a2 : signed(15 downto 0) := to_signed(15426,16)		-- a2 = 0,91498813  -> a2*2^14 = 15426
	);
	port
	(
		clk : in std_logic;
		n_reset : in std_logic;
		--clk_en : in std_logic;
		u : in signed(11 downto 0); -- Eingang
		x : out signed(11 downto 0) -- Ausgang
	);

end entity;

architecture rtl of filter is

    signal xa, xb   : signed(27 downto 0);
    signal x_int    : signed(11 downto 0);

begin

    process
	variable xk : signed(27 downto 0);
	begin
        wait until rising_edge(clk);

        if n_reset = '0' then
            xa <= (others => '0');
            xb <= (others => '0');
            x_int <= (others => '0');
        else
            -- Rekursionsformel: x = b0*u + b1*u + b2*u - a1*x - a2*x
            xa <= b2*u - a2*x_int;
            xb <= xa + b1*u - a1*x_int;
            
            xk := (xb + b0*u) / 16384;
            x_int <= xk(11 downto 0);
            --x_int <= xk(13 downto 2);
		end if;
	end process;

    x <= x_int;

end architecture rtl;