library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity filter_tb is
end entity filter_tb;

architecture testbench of filter_tb is

    signal simulation_run   : boolean   := true;
    constant clk_period     : time      := 1 sec / 10_000_000;

    signal tb_clk       : std_logic   := '0';
    signal tb_n_reset   : std_logic;
    signal tb_u         : signed(11 downto 0)   := (others => '0');
    signal tb_x         : signed(11 downto 0);

begin

    tb_clk      <= not tb_clk after clk_period / 2 when simulation_run;
    tb_n_reset  <= '0', '1' after 5 * clk_period;

    tb_u    <= tb_u + 1 when falling_edge( tb_clk) and tb_n_reset = '1';

    dut: entity work.filter
	port map
	(
		clk     => tb_clk,      -- : in std_logic;
		n_reset => tb_n_reset,  -- : in std_logic;
        --
		u       => tb_u,        -- : in    signed(11 downto 0); -- Eingang
		x       => tb_x         -- : inout signed(11 downto 0) -- Ausgang
	);

    process
    begin
        wait for 2 ms;
        simulation_run  <= false;
        report "Simulation end.";
        wait; -- forever
    end process;


end architecture testbench;