library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity filter is
	generic
	(  -- Q = 14
		b0                             : signed(15 downto 0) := to_signed(16,16);     -- b0 = 0,00094469  -> b0*2^14 = 16
		b1                             : signed(15 downto 0) := to_signed(31,16);     -- b1 = 0,00188940  -> b1*2^14 = 31
		b2                             : signed(15 downto 0) := to_signed(62,16);     -- b2 = b0
		a1                             : signed(15 downto 0) := to_signed(-31313,16); -- a1 = -1,91120934 -> a1*2^14 = -31313
		a2                             : signed(15 downto 0) := to_signed(15426,16)   -- a2 = 0,91498813  -> a2*2^14 = 15426
	);
	port
	(
		clk                            : in std_logic;
		n_reset                        : in std_logic;
		sample_in                      : in signed(11 downto 0); -- Eingang
		sample_out                     : out signed(11 downto 0) -- Ausgang
	);
end entity;

architecture rtl of filter is

signal x                               : signed(27 downto 0) := (others => '0');
signal xa                              : signed(27 downto 0) := (others => '0');
signal xb                              : signed(27 downto 0) := (others => '0');

begin

process (clk) begin
	if rising_edge(clk) then
		sample_out <= x(19 downto 8);
		if n_reset = '0' then
			xa <= (others => '0');
			xb <= (others => '0');
		else
			-- Rekursionsformel: x = b0*sample_in + b1*sample_in + b2*sample_in - a1*x - a2*x
			xa <= b2*sample_in - a2*x(27 downto 16);
			xb <= xa + b1*sample_in - a1*x(27 downto 16);
			x <= xb + b0*sample_in;
		end if;
	end if;
end process;

end rtl;