library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.math_real.all; entity tb_filter is end entity; architecture tb of tb_filter is type rom1kx12 is array (0 to 1023) of signed(11 downto 0); signal sinus_rom : rom1kx12; signal clk : std_logic := '1'; signal adr : unsigned(9 downto 0) := (others => '0'); signal samplecounter : integer range 0 to 127 := 0; signal speed : unsigned(8 downto 0) := "000000001"; signal sample_in : signed(11 downto 0) := (others => '0'); signal sample_out : signed(11 downto 0) := (others => '0'); begin tabel : for I in 0 to 1023 generate sinus_rom(I) <= to_signed(integer(sin(2.0*MATH_PI*(real(I)+0.5)/1024.0)*2047.5),12); end generate; clk <= not clk after 5 ns; process begin wait until falling_edge(clk); if samplecounter < 127 then samplecounter <= samplecounter +1; else samplecounter <= 0; if speed < 500 then speed <= speed +5; end if; end if; adr <= adr + speed; sample_in <= sinus_rom(to_integer(adr)); end process; inst_filter : entity work.filter generic map ( -- Q = 14 b0 => to_signed(16,16), -- b0 = 0,00094469 -> b0*2^14 = 16 b1 => to_signed(31,16), -- b1 = 0,00188940 -> b1*2^14 = 31 b2 => to_signed(62,16), -- b2 = b0 a1 => to_signed(-31313,16), -- a1 = -1,91120934 -> a1*2^14 = -31313 a2 => to_signed(15426,16) -- a2 = 0,91498813 -> a2*2^14 = 15426 ) port map ( clk => clk, n_reset => '1', sample_in => sample_in, -- Eingang sample_out => sample_out -- Ausgang ); end;