library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity filter is
	generic
	(  -- Q = 14
		b0 : signed(15 downto 0) := to_signed(16*8,16);     -- b0 = 0,00094469  -> b0*2^14 = 16
		b1 : signed(15 downto 0) := to_signed(32*8,16);     -- b1 = 0,00188940  -> b1*2^14 = 31
		b2 : signed(15 downto 0) := to_signed(16*8,16);     -- b2 = b0
		a1 : signed(15 downto 0) := to_signed(-31313,16); -- a1 = -1,91120934 -> a1*2^14 = -31313
		a2 : signed(15 downto 0) := to_signed(14991,16)   -- a2 = 0,91498813  -> a2*2^14 = 14991
	);
	port
	(
		clk : in std_logic;
		n_reset : in std_logic;
		u : in signed(11 downto 0); -- Eingang
		x : out signed(15 downto 0) -- Ausgang
	);
end entity;

architecture rtl of filter is
signal xk : signed(15 downto 0) := (others => '0');
signal s2 : signed(31 downto 0) := (others => '0');
signal s1 : signed(31 downto 0) := (others => '0');
begin
process (clk,xk)
	variable xtemp : signed(31 downto 0) ;
	begin
	if rising_edge(clk) then
		if n_reset = '0' then
			s1 <= (others => '0');
			s2 <= (others => '0');
			xk <= (others => '0');
		else
			-- Rekursionsformel: x = b0*u + b1*u + b2*u - a1*x - a2*x
			s2 <=         b2 * u + to_signed(0,32) ;
			s1 <=    s2 + b1 * u - a2 * xk;
			xtemp := s1 + b0 * u - a1 * xk;
			
			if ( xtemp(29 downto 14) > 32767 ) then
			    xk <= to_signed(32767,16) ;
			elsif ( xtemp(29 downto 14) < -32768 ) then
			    xk <= to_signed(-32768,16) ;
			else 
				 xk <= xtemp(29 downto 14) ; -- Saturation 
			end if ;
			
		end if;
	end if;
	x <= xk; -- 19 downto 8
end process;
end rtl;