/* SPI Initialsierung und ISR des SLAVE */

#define ARRAY_LEN 22				/* Laenge der rec_ und sen_byte Arrays */

/* Initialization Slave Mode (interrupt controlled) */
static void init_SLAVE_INT(void) {
	volatile char IOReg;
	DDRB &= ~((1<<PB3)|(1<<PB5)|(1<<PB2));		/* MOSI, SCK, SS as input */
	DDRB |= (1<<PB4);							/* Set PB4(MISO) as output */
	PORTB |= (1<<PB2);							/* activate PullUp of PB2 as it's an input */
	SPCR  = (1<<SPIE)|(1<<SPE);					/* SPI INT, SPI enable, Slave */
	IOReg = SPSR;								/* Clear SPIF bit in SPSR */
	IOReg = SPDR;
}

/* ISR - Read/Write SPI Data, Slave, interrupt controlled*/
ISR(SPI_STC_vect) {
	volatile uint8_t data;			/* Zwischenspeicher - noetig??? */
	if(i_spi == 0)SPDR = sen_byte[0];		/* schreib Byte[0] ins SPDR */
	PORTD |= (1<<PD4);				/* Ausgang "HIGH" -> Master PD3 Eingang = "HIGH"*/
	if(i_spi < ARRAY_LEN) {			/* Arraylaenge noch nicht erreicht */
		data=SPDR;					/* lies & speicher die SPDR Daten in data */
		rec_byte[i_spi]=data;		/* speicher data in Empfangspeicher */
		i_spi++;					/* zaehle weiter */
		if(i_spi >= ARRAY_LEN) {
			empfang = 1;			/* Arraylaenge ereicht */
		} else {
			SPDR = sen_byte[i_spi];		/* zu sendende Daten in SPDR schreiben */
		}
		PORTD &= ~(1<<PD4);			/* Ausgang LOW -> Master = "0" = INT1 = "1" */
	}
}