/* SPI Initialisierung und polling des Masters */

#define ARRAY_LEN 22				/* Laenge der rec_ und sen_byte Arrays */
#define SPI_MON 6					/* Ueberwachungszeit SPI Antwort Slave */

static uint8_t sen_byte[ARRAY_LEN];				/* per SPI uebertragene Daten */
static uint8_t rec_byte[ARRAY_LEN];				/* per SPI empfangene Daten */

/* initialisieren Interrupts INT0 und INT1 beim Master */
static void init_interrupt(void) {
	EXT_INT_FLA |= (1 << ISC01)|(1 << ISC11);	/* INT0/INT1 Trigger fallende Flanke */
	EXT_INT_ACT |= (1 << INT0)|(1 << INT1);		/* INT0/INT1 aktivieren => PD2, PD3 */
}

/* ISR INT1 => HW-Signal vom Slave PD4 -> PD3 Master => Signal fuer SPI */
ISR(INT1_vect) {
	slave_frg = 1;		/* Slave gibt SPI frei */
}

/* Initialization Master Mode (polling) */
static void init_SPI_MASTER_poll(void) {
	volatile char IOReg;
	DDRB |= (1<<PB2)|(1<<PB3)|(1<<PB5);		/* PB2(/SS), PB3(MOSI), PB5(SCK) output */
	DDRB &= ~(1<<PB4);						/* Make PB4(MISO) Pin as input Pin */
	PORTB |= (1<<PB2);						/* Disable Slave => high on SS Pin */
	SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); 	/* SPI Master Mode, SCK = CK/16 */
	IOReg = SPSR;							/* Clear SPIF bit in SPSR */
	IOReg = SPDR;
}

/* Read/Write SPI Data, Master, polling in main() cyclic after 30 ms */
static uint8_t SPI_write( void ) {
	uint8_t zaehler;
	uint8_t spi_fehler;
	zaehler = 0;
	spi_fehler = 0;

	PORTB &= ~(1<<PB2);						/* Slave enable */
	__asm volatile("nop");					/* just wait ... */

	SPDR = sen_byte[zaehler];				/* Sendewert => SPDR */
	while(zaehler < ARRAY_LEN) {			/* Abbruch */
		while(!(SPSR & (1<<SPIF))); 		/* warten auf Uebertragung fertig */
		rec_byte[zaehler] = SPDR;			/* Empfangswert in Empfangsspeicher */
		zaehler++;							/* Zaehler weiter zaehlen */
		zaehler3_t0 = 0;
		while((!slave_frg)&&(zaehler3_t0 < SPI_MON));	/* Slave PD4 = "1" - warte => INT1!! */
		if(!slave_frg) {
			PORT_ON(PORTD, PD7);	/* Slave antwortet nicht */
			spi_fehler = 1;
			zaehler = ARRAY_LEN;
		}
		SPDR = sen_byte[zaehler];			/* Sendewert vom Sendespeicher */
		slave_frg = 0;
	}
	while(!(SPSR & (1<<SPIF)));				/* warten auf fertig */
	PORTB |= (1<<PB2);						/* Slave disable */
	return spi_fehler;						/* 0 = kein Fehler, 1 = Fehler */
}