library ieee;
use ieee.std_logic_1164.all;

entity RECH_POLY is
  port
    (INP, RESET, CLOCK : in std_logic;
     ERGEBNIS : out std_logic_vector(9 downto 0));
end entity RECH_POLY;

architecture BERECHNUNG of RECH_POLY is
    signal R : std_logic_vector(9 downto 0);
    signal ZS : std_logic;
    signal count : natural := 9;

begin

  process (CLOCK, RESET) is

  begin
    if RESET = '1' then
      R <= "0000000001";
      count <= 9;
    else
      if rising_edge(CLOCK) then
        ZS <= INP xor R(7) xor R(6) xor R(5) xor R(3);
        R <= ZS & R(7 downto 1);
      end if;
    end process;

   ERGEBNIS  <= R;
    
  end architecture BERECHNUNG of RECH_POLY;