--Copyright 2023, Xaver Xanthus
--for educational purposes only
--Revision0.02

library ieee;
use ieee.std_logic_1164.all;

entity e_lfsr is
  port
    (inp_i, rst_i, clk_i : in  std_logic;
     res_o               : out std_logic_vector(9 downto 0));
end entity e_lfsr;

architecture behave of e_lfsr is
  signal s_reg  : std_logic_vector(9 downto 0);
  signal s_zs : std_logic;

begin

  process (clk_i, rst_i) is
  begin
    if rst_i = '1' then
      s_reg     <= "0000000001";
    else
      if rising_edge(clk_i) then
        s_zs <= inp_i xor s_reg(7) xor s_reg(6) xor s_reg(5) xor s_reg(3);
        s_reg  <= s_zs & s_reg(7 downto 1);
      end if;
    end if;
  end process;

  res_o <= s_reg;

end architecture behave;