-------------------------------------------------------------------------------
-- Title      : Polynom division
-- Project    : 
-------------------------------------------------------------------------------
-- File       : poly_mult.vhd
-- Author     :   
-- Company    : 
-- Created    : 2023-01-03
-- Last update: 2023-01-03
-- Platform   : 
-- Standard   : VHDL'93/02
-------------------------------------------------------------------------------
-- Description:  Hausaufgabe
-------------------------------------------------------------------------------
-- Copyright (c) 2023, educational purposes only 
-------------------------------------------------------------------------------
-- Revisions  :
-- Date        Version  Author          Description
-- 2023-01-03  0.04      Xaver Xanthus  based on gustl work, transformed from testbench, adopted to industry naming and style conventions
--                                      expect functionale changes from poor documentation, sub-optimal identifiernaming and vector direction reversal  
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity e_polymult is
  port (
    clk_i  : in  std_logic;
    arst_i : in  std_logic;
    --
    inp_i  : in  std_logic;
    res_o  : out std_logic_vector(11 downto 0));
end entity e_polymult;

architecture behave of e_polymult is

  --signal s_inp_q : std_logic_vector(11 downto 0);
  signal reg_q   : std_logic_vector(7 downto 0);

  signal s_inp   : std_logic;           -- consider 'alias' during refactoring
  signal s_out_2 : std_logic;

  signal s_out_q : std_logic_vector(11 downto 0);

begin
  --s_inp   <= s_inp_q(0);

  process(clk_i, arst_i)
  begin
    if arst_i = '1' then
      reg_q   <= "110100000000";
      --s_out_q <= (others => '0');
      --s_inp_q <= (others => '0');
    else
      if rising_edge(clk_i) then
        --s_inp_q <= '0' & s_inp_q(11 downto 1);

        reg_q(0) <= inp_i;
        reg_q(1) <= reg_q(0) xor inp_i;
        reg_q(2) <= reg_q(1) xor inp_i;
        reg_q(3) <= reg_q(2);
        reg_q(4) <= reg_q(3) xor inp_i;
        reg_q(5) <= reg_q(4);
        reg_q(6) <= reg_q(5);
        reg_q(7) <= reg_q(6) xor inp_i;
        --s_out_q  <= s_out_2 & s_out_q(11 downto 1);
      end if;
    end if;
  end process;

  res_o <= reg_q(7) xor inp_i;

  
end;