library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity berlinuhr is
    Port ( clk32k : in  STD_LOGIC;
           setslow: in  STD_LOGIC;
           setfast: in  STD_LOGIC;
           sec    : out STD_LOGIC;
           min    : buffer STD_LOGIC_VECTOR (3 downto 0)  := (others=>'0');
           min5   : buffer STD_LOGIC_VECTOR (10 downto 0) := (others=>'0');
           hr     : buffer STD_LOGIC_VECTOR (3 downto 0)  := (others=>'0');
           hr5    : buffer STD_LOGIC_VECTOR (3 downto 0)  := (others=>'0') );
end berlinuhr;

architecture verhalten of berlinuhr is

signal cpresc : unsigned (15+6 downto 0) := (others=>'0');
signal cntup  : std_logic;

begin
  
   process begin
      wait until rising_edge(clk32k);
      cntup <= '0';
      if (setslow='1' and cpresc(15)='1')       -- langsam stellen
      or (setfast='1' and cpresc(11)='1')       -- schnell stellen
      or (cpresc = to_unsigned(32768*60-1, 22)) -- Minute vorbei
      then
         cntup <= '1';
         cpresc <= (others=>'0');
      else 
         cpresc <= cpresc + 1;
      end if;
   end process;
   
   process begin
      wait until rising_edge(clk32k);
      if cntup='1' then
         min <= min(2 downto 0) & '1'; 
         if min(3)='1' then
            min <= (others=>'0');
            min5 <= min5(9 downto 0) & '1'; 
            if min5(10) = '1' then
               min5 <= (others=>'0');
               hr   <= hr(2 downto 0) & '1';
               if hr(3) = '1' then
                  hr  <= (others=>'0');
                  hr5 <= hr5(2 downto 0) & '1';
               end if;
               if hr5(3)='1' and hr(2)='1' then -- Tagesüberlauf extra und bevorzugt abhandeln
                  hr  <= (others=>'0');
                  hr5 <= (others=>'0');
               end if;
            end if;
         end if;
      end if;
   end process;
   
   sec  <= cpresc(15);
  
end verhalten;