.nolist
.include "tn13adef.inc" ; Define device ATtiny13A
.list
.def sreg_bak = R15 
.def rmp = R16 

.dseg
.org SRAM_START
.cseg
.org 0x0000
rjmp Main ; Reset vector
reti ; INT0
reti ; PCI0
rcall isr_timer_overflow ; OVF0
reti ; ERDY
reti ; ACI
reti; isr_oc0a; OC0A
reti; rcall isr_oc0b; OC0B
rcall isr_watchdog ; WDT
reti ; ADCC


init_watchdog:
 wdr
 in rmp, MCUSR
 andi rmp, (0xff - (1<<WDRF))
 out MCUSR, rmp
 in rmp, WDTCR
 ori rmp, (1<<WDTIE)|(1<<WDP0) ; prescaler 32ms
 out WDTCR, rmp
 ret

init_timer0:
 push rmp
 ldi rmp, 220
 out OCR0B, rmp
 ldi rmp,(1<<WGM01)
 out TCCR0A, rmp
 ldi rmp, (1<<CS01)
 out TCCR0B, rmp
 ldi rmp, (1<<TOIE0)
 out TIMSK0, rmp
 pop rmp
 ret


Main:
 ldi rmp,Low(RAMEND)
 out SPL,rmp ; Init LSB stack pointer
 rcall init_watchdog
 rcall init_timer0
 sbi DDRB,1
 sei ; Enable interrupts


Loop:
  nop
  rjmp Loop


isr_timer_overflow:
 in sreg_bak, SREG
 cbi PORTB,1
 ;rcall disable_overflow
 out SREG, sreg_bak
 reti

isr_watchdog:
 in sreg_bak, SREG
 sbi PORTB,1
 ;rcall enable_overflow
 out SREG, sreg_bak
 reti

;enable_overflow:
; push rmp
; ldi rmp, 0
; out TCNT0, rmp
; in rmp, TIMSK0
; ori rmp, (1<<TOIE0)
; out TIMSK0, rmp
; pop rmp
; ret
;
;disable_overflow:
; push rmp
; in rmp, TIMSK0
; andi rmp, (0<<TOIE0)
; out TIMSK0, rmp
; pop rmp
; ret

;enable compare_b:
; push rmp
; in rmp,TIMSK0
; andi rmp, (1<<OCIE0B)
; out TIMSK0, rmp
; pop rmp
; ret
;
;disable_compare_b:
; push rmp
; in rmp,TIMSK0
; andi rmp, (0<<OCIE0B)
; out TIMSK0, rmp
; pop rmp
; ret