-- SubModule LogicVHLD_1
-- Created   Test 
--------------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TEST_PROJ is port
   (
    LED1 : out    std_logic;
    LED2 : out    std_logic;
	LED3 : out    std_logic;
	TASTER1 : in  std_logic;
	TASTER2 : in  std_logic;
	TASTER3	: in  std_logic
    );
end TEST_PROJ;



architecture Structure1 of TEST_PROJ is

begin 	

	LED1 <= TASTER1;

end Structure1;



architecture Structure2 of TEST_PROJ is

begin 	

	LED2 <= TASTER2;

end Structure2;