Lattice Synthesis Timing Report
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Lattice Synthesis Timing Report, Version  
Fri Jun 21 22:37:22 2024

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Design:     TEST_PROJ
Constraint file:  
Report level:    verbose report, limited to 3 items per constraint
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Timing Report Summary
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Constraint                              |   Constraint|       Actual|Levels
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                                        |             |             |
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All constraints were met.



Timing summary:
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Timing errors: 0  Score: 0

Constraints cover  0 paths, 0 nets, and 0 connections (0.0% coverage)


Peak memory: 77623296 bytes, TRCE: 1134592 bytes, DLYMAN: 0 bytes
CPU_TIME_REPORT: 0 secs