Lattice Mapping Report File for Design Module 'TEST_PROJ'



Design Information

Command line:   map -a MachXO2 -p LCMXO2-7000HC -t TQFP144 -s 5 -oc Commercial
     TestFPGA01_impl1_Trest01.ngd -o TestFPGA01_impl1_Trest01_map.ncd -pr
     TestFPGA01_impl1_Trest01.prf -mp TestFPGA01_impl1_Trest01.mrp -lpf
     C:/lscc/Examples RP/Test_01/impl1_Trest01/TestFPGA01_impl1_Trest01.lpf -lpf
     C:/lscc/Examples RP/Test_01/TestFPGA01.lpf -c 0 -gui 
Target Vendor:  LATTICE
Target Device:  LCMXO2-7000HCTQFP144
Target Performance:   5
Mapper:  xo2c00,  version:  Diamond (64-bit) 3.13.0.56.2
Mapped on:  06/21/24  22:37:22


Design Summary
   Number of registers:      0 out of  7209 (0%)
      PFU registers:            0 out of  6864 (0%)
      PIO registers:            0 out of   345 (0%)
   Number of SLICEs:         1 out of  3432 (0%)
      SLICEs as Logic/ROM:      1 out of  3432 (0%)
      SLICEs as RAM:            0 out of  2574 (0%)
      SLICEs as Carry:          0 out of  3432 (0%)
   Number of LUT4s:          1 out of  6864 (0%)
      Number used as logic LUTs:          1
      Number used as distributed RAM:     0
      Number used as ripple logic:        0
      Number used as shift registers:     0
   Number of PIO sites used: 4 + 4(JTAG) out of 115 (7%)
   Number of block RAMs:  0 out of 26 (0%)
   Number of GSRs:        0 out of 1 (0%)
   EFB used :        No
   JTAG used :       No
   Readback used :   No
   Oscillator used : No
   Startup used :    No
   POR :             On
   Bandgap :         On
   Number of Power Controller:  0 out of 1 (0%)
   Number of Dynamic Bank Controller (BCINRD):  0 out of 6 (0%)
   Number of Dynamic Bank Controller (BCLVDSO):  0 out of 1 (0%)
   Number of DCCA:  0 out of 8 (0%)
   Number of DCMA:  0 out of 2 (0%)
   Number of PLLs:  0 out of 2 (0%)
   Number of DQSDLLs:  0 out of 2 (0%)
   Number of CLKDIVC:  0 out of 4 (0%)
   Number of ECLKSYNCA:  0 out of 4 (0%)
   Number of ECLKBRIDGECS:  0 out of 2 (0%)
   Notes:-
      1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of
     distributed RAMs) + 2*(Number of ripple logic)
      2. Number of logic LUT4s does not include count of distributed RAM and
     ripple logic.
   Number of clocks:  0
   Number of Clock Enables:  0
   Number of LSRs:  0
   Number of nets driven by tri-state buffers:  0

   Top 10 highest fanout non-clock nets:
     Net LED2_c_c: 1 loads




   Number of warnings:  4
   Number of errors:    0
     




Design Errors/Warnings

WARNING - map: input pad net 'TASTER1' has no legal load.
WARNING - map: input pad net 'TASTER3' has no legal load.
WARNING - map: IO buffer missing for top level port TASTER1...logic will be
     discarded.
WARNING - map: IO buffer missing for top level port TASTER3...logic will be
     discarded.



IO (PIO) Attributes

+---------------------+-----------+-----------+------------+
| IO Name             | Direction | Levelmode | IO         |
|                     |           |  IO_TYPE  | Register   |
+---------------------+-----------+-----------+------------+
| LED1                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED2                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| LED3                | OUTPUT    | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+
| TASTER2             | INPUT     | LVCMOS25  |            |
+---------------------+-----------+-----------+------------+



Removed logic

Block i12 undriven or does not drive anything - clipped.
Block GSR_INST undriven or does not drive anything - clipped.
Signal VCC_net undriven or does not drive anything - clipped.

     



Run Time and Memory Usage
-------------------------

   Total CPU Time: 0 secs  
   Total REAL Time: 0 secs  
   Peak Memory Usage: 36 MB
        







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