PAR: Place And Route Diamond (64-bit) 3.13.0.56.2.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 21 22:37:23 2024

C:/lscc/diamond/3.13/ispfpga\bin\nt64\par -f TestFPGA01_impl1_Trest01.p2t
TestFPGA01_impl1_Trest01_map.ncd TestFPGA01_impl1_Trest01.dir
TestFPGA01_impl1_Trest01.prf -gui


Preference file: TestFPGA01_impl1_Trest01.prf.

Cost Table Summary
Level/       Number       Worst        Timing       Worst        Timing       Run          NCD
Cost [ncd]   Unrouted     Slack        Score        Slack(hold)  Score(hold)  Time         Status
----------   --------     -----        ------       -----------  -----------  ----         ------
5_1   *      0            -            -            -            -            02           Completed
* : Design saved.

Total (real) run time for 1-seed: 2 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Lattice Place and Route Report for Design "TestFPGA01_impl1_Trest01_map.ncd"
Fri Jun 21 22:37:23 2024


Best Par Run
PAR: Place And Route Diamond (64-bit) 3.13.0.56.2.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -gui -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF:parASE=1 TestFPGA01_impl1_Trest01_map.ncd TestFPGA01_impl1_Trest01.dir/5_1.ncd TestFPGA01_impl1_Trest01.prf
Preference file: TestFPGA01_impl1_Trest01.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file TestFPGA01_impl1_Trest01_map.ncd.
Design name: TEST_PROJ
NCD version: 3.3
Vendor:      LATTICE
Device:      LCMXO2-7000HC
Package:     TQFP144
Performance: 5
Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status:                     Final          Version 1.39.
Performance Hardware Data Status:   Final          Version 34.4.
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)    4+4(JTAG)/336     2% used
                   4+4(JTAG)/115     7% bonded

   SLICE              1/3432         <1% used



Number of Signals: 2
Number of Connections: 3

Pin Constraint Summary:
   0 out of 4 pins locked (0% locked).

No signal is selected as primary clock.


No signal is selected as secondary clock.

No signal is selected as Global Set/Reset.
.
Starting Placer Phase 0.
.......
Finished Placer Phase 0.  REAL time: 0 secs 

Starting Placer Phase 1.
..
Placer score = 500413.
Finished Placer Phase 1.  REAL time: 0 secs 

Starting Placer Phase 2.
.
Placer score =  500413
Finished Placer Phase 2.  REAL time: 0 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  PLL        : 0 out of 2 (0%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Global Clocks:

  PRIMARY  : 0 out of 8 (0%)
  SECONDARY: 0 out of 8 (0%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   4 + 4(JTAG) out of 336 (2.4%) PIO sites used.
   4 + 4(JTAG) out of 115 (7.0%) bonded PIO sites used.
   Number of PIO comps: 4; differential: 0.
   Number of Vref pins used: 0.

I/O Bank Usage Summary:
+----------+---------------+------------+-----------+
| I/O Bank | Usage         | Bank Vccio | Bank Vref |
+----------+---------------+------------+-----------+
| 0        | 0 / 28 (  0%) | -          | -         |
| 1        | 0 / 29 (  0%) | -          | -         |
| 2        | 1 / 29 (  3%) | 2.5V       | -         |
| 3        | 3 / 9 ( 33%)  | 2.5V       | -         |
| 4        | 0 / 10 (  0%) | -          | -         |
| 5        | 0 / 10 (  0%) | -          | -         |
+----------+---------------+------------+-----------+

Total placer CPU time: 0 secs 

Dumping design to file TestFPGA01_impl1_Trest01.dir/5_1.ncd.


-----------------------------------------------------------------
INFO - par: ASE feature is off due to non timing-driven settings.  
-----------------------------------------------------------------

0 connections routed; 3 unrouted.
Starting router resource preassignment

Completed router resource preassignment. Real time: 0 secs 

Start NBR router at 22:37:24 06/21/24

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design.                                               
*****************************************************************

Start NBR special constraint process at 22:37:24 06/21/24

Start NBR section for initial routing at 22:37:24 06/21/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Info: Initial congestion level at 75% usage is 0
Info: Initial congestion area  at 75% usage is 0 (0.00%)

Start NBR section for normal routing at 22:37:24 06/21/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Start NBR section for re-routing at 22:37:24 06/21/24
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 0 (nbr) score; real time: 0 secs 

Start NBR section for post-routing at 22:37:24 06/21/24

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 0 (0.00%)
  Estimated worst slack<setup> : <n/a>
  Timing score<setup> : 0
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



Total CPU time 1 secs 
Total REAL time: 0 secs 
Completely routed.
End of route.  3 routed (100.00%); 0 unrouted.

Hold time timing score: 0, hold timing errors: 0

Timing score: 0 

Dumping design to file TestFPGA01_impl1_Trest01.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = Completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack<setup/<ns>> = <n/a>
PAR_SUMMARY::Timing score<setup/<ns>> = <n/a>
PAR_SUMMARY::Worst  slack<hold /<ns>> = <n/a>
PAR_SUMMARY::Timing score<hold /<ns>> = <n/a>
PAR_SUMMARY::Number of errors = 0

Total CPU  time to completion: 1 secs 
Total REAL time to completion: 2 secs 

par done!

Note: user must run 'Trace' for timing closure signoff.

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.