Synthesis and Ngdbuild Report

Synthesis and Ngdbuild  Report
synthesis:  version Diamond (64-bit) 3.13.0.56.2

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Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2023 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 21 22:37:22 2024


Command Line:  synthesis -f TestFPGA01_impl1_Trest01_lattice.synproj -gui 

Synthesis options:
The -a option is MachXO2.
The -s option is 5.
The -t option is TQFP144.
The -d option is LCMXO2-7000HC.
Using package TQFP144.
Using performance grade 5.
                                                          

##########################################################

### Lattice Family : MachXO2

### Device  : LCMXO2-7000HC

### Package : TQFP144

### Speed   : 5

##########################################################

                                                          

INFO - synthesis: User-Selected Strategy Settings
Optimization goal = Balanced
The -top option is not used.
Target frequency = 200.000000 MHz.
Maximum fanout = 1000.
Timing path count = 3
BRAM utilization = 100.000000 %
DSP usage = true
DSP utilization = 100.000000 %
fsm_encoding_style = auto
resolve_mixed_drivers = 0
fix_gated_clocks = 1

Mux style = Auto
Use Carry Chain = true
carry_chain_length = 0
Loop Limit = 1950.
Use IO Insertion = TRUE
Use IO Reg = AUTO

Resource Sharing = TRUE
Propagate Constants = TRUE
Remove Duplicate Registers = TRUE
force_gsr = auto
ROM style = auto
RAM style = auto
The -comp option is FALSE.
The -syn option is FALSE.
-p C:/lscc/diamond/3.13/ispfpga/xo2c00/data (searchpath added)
-p C:/lscc/Examples RP/Test_01/impl1_Trest01 (searchpath added)
-p C:/lscc/Examples RP/Test_01 (searchpath added)
VHDL library = work
VHDL design file = C:/lscc/Examples RP/Test_01/TestVDHL_MainSheet.vhdl
NGD file = TestFPGA01_impl1_Trest01.ngd
-sdc option: SDC file input not used.
-lpf option: Output file option is ON.
Hardtimer checking is enabled (default). The -dt option is not used.
The -r option is OFF. [ Remove LOC Properties is OFF. ]
Technology check ok...

Analyzing Verilog file C:/lscc/diamond/3.13/ispfpga/userware/NT/SYNTHESIS_HEADERS/machxo2.v. VERI-1482
Compile design.
Compile Design Begin
WARNING - synthesis: Setting TEST_PROJ as the top-level module. To specify the top-level module explicitly, use the -top option.
INFO - synthesis: The default VHDL library search path is now "C:/lscc/Examples RP/Test_01/impl1_Trest01". VHDL-1504
Analyzing VHDL file c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl. VHDL-1481
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(9): analyzing entity test_proj. VHDL-1012
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(22): analyzing architecture structure1. VHDL-1010
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(32): analyzing architecture structure2. VHDL-1010
unit TEST_PROJ is not yet analyzed. VHDL-1485
Analyzing VHDL file c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl. VHDL-1481
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(9): analyzing entity test_proj. VHDL-1012
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(22): analyzing architecture structure1. VHDL-1010
INFO - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(32): analyzing architecture structure2. VHDL-1010
unit TEST_PROJ is not yet analyzed. VHDL-1485
unit TEST_PROJ is not yet analyzed. VHDL-1485
c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(9): executing TEST_PROJ(Structure2)

WARNING - synthesis: c:/lscc/examples rp/test_01/testvdhl_mainsheet.vhdl(18): replacing existing netlist TEST_PROJ(Structure2). VHDL-1205
Top module name (VHDL): TEST_PROJ
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'...
Loading device for application map from file 'xo2c7000.nph' in environment: C:/lscc/diamond/3.13/ispfpga.
Package Status:                     Final          Version 1.39.
Top-level module name = TEST_PROJ.
WARNING - synthesis: I/O Port LED1 's net has no driver and is unused.
WARNING - synthesis: I/O Port LED2 's net has no driver and is unused.
WARNING - synthesis: I/O Port LED3 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER1 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER2 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER3 's net has no driver and is unused.
######## Missing driver on net LED1. Patching with GND.
######## Missing driver on net LED3. Patching with GND.



WARNING - synthesis: I/O Port LED2 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER1 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER2 's net has no driver and is unused.
WARNING - synthesis: I/O Port TASTER3 's net has no driver and is unused.
GSR will not be inferred because no asynchronous signal was found in the netlist.
Applying 200.000000 MHz constraint to all clocks

WARNING - synthesis: No user .sdc file.
Results of NGD DRC are available in TEST_PROJ_drc.log.
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00a/data/xo2alib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/xo2c00/data/xo2clib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/mg5g00/data/mg5glib.ngl'...
Loading NGL library 'C:/lscc/diamond/3.13/ispfpga/or5g00/data/orc5glib.ngl'...
WARNING - synthesis: logical net 'TASTER1' has no load.
WARNING - synthesis: input pad net 'TASTER1' has no legal load.
WARNING - synthesis: logical net 'TASTER3' has no load.
WARNING - synthesis: input pad net 'TASTER3' has no legal load.
WARNING - synthesis: DRC complete with 4 warnings.
All blocks are expanded and NGD expansion is successful.
Writing NGD file TestFPGA01_impl1_Trest01.ngd.

################### Begin Area Report (TEST_PROJ)######################
Number of register bits => 0 of 7209 (0 % )
GSR => 1
IB => 1
OB => 3
################### End Area Report ##################

################### Begin BlackBox Report ######################
TSALL => 1
################### End BlackBox Report ##################

################### Begin Clock Report ######################
Clock Nets
Number of Clocks: 0
Clock Enable Nets
Number of Clock Enables: 0
Top 0 highest fanout Clock Enables:
Highest fanout non-clock nets
Top 10 highest fanout non-clock nets:
  Net : LED2_c_c, loads : 1
  Net : LED2, loads : 0
  Net : LED1, loads : 0
  Net : LED3, loads : 0
################### End Clock Report ##################

Peak Memory Usage: 74.477  MB

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Elapsed CPU time for LSE flow : 0.328  secs
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