-- Version 20240623_07:14 -- (Lieutenant Junior Grade) Bradward Boimler -- SubModule LogicVHLD_1 -- Created Test -------------------------------------------------------------------------------- library IEEE; use IEEE.Std_Logic_1164.all; --use IEEE.STD_LOGIC_UNSIGNED.all; entity e_3led3tast is port ( LED1 : out std_logic; LED2 : out std_logic; LED3 : out std_logic; TASTER1 : in std_logic; TASTER2 : in std_logic; TASTER3 : in std_logic); end e_3led3tast; architecture Structure1 arch_ledtast1 of e_3led3tast is begin LED1 <= TASTER1; LED2 <= '0'; LED3 <= '1'; end arch_ledtast1; architecture arch_ledtast2 of e_3led3tast is begin LED1 <= '0'; LED2 <= TASTER2; LED3 <= '1'; end arch_ledtast2; --now comes the top which use the different components --this shall be placed in an extra VHDL source-file library IEEE; use IEEE.Std_Logic_1164.all; --use IEEE.STD_LOGIC_UNSIGNED.all; use work.all; entity e_top is port ( LED_o : out std_logic_vector(6 downto 1); TASTER_i : in std_logic_vector(3 downto 1)); end e_top; architecture arch_top is component comp_3led3tast is port ( LED1 : out std_logic; LED2 : out std_logic; LED3 : out std_logic; TASTER1 : in std_logic; TASTER2 : in std_logic; TASTER3 : in std_logic); end component comp_3led3tast; begin i_3led3tast_1 : comp_3led3tast port map ( LED1 => LED_o(1), LED2 => LED_o(2), LED3 => LED_o(3), TASTER1 => TASTER_i(1), TASTER2 => TASTER_i(2), TASTER3 => TASTER_i(3)); i3led3tast_2 : comp_3led3tast port map ( LED1 => LED_o(4), LED2 => LED_o(5), LED3 => LED_o(6), TASTER1 => TASTER_i(1), TASTER2 => TASTER_i(2), TASTER3 => TASTER_i(3)); end architecture; configuration cnf1 of e_top is for arch_top for i_3led3tast_1 : comp_3led3tast use entity work.e_3led3tast(arch_ledtast1); end for; for i_3led3tast_2 : comp_3led3tast use entity work.e_3led3tast(arch_ledtast2); end for; end for; end configuration cnf1;