----------------------------------------------------------------------------------
-- Company:Zuritronic 
-- Engineer:a.Kurka 
--
-- Create Date:   06.05.2021 by a.kurka
-- Design Name: 		AS21
-- Module Name:    arccos - Behavioral 
--  modified : 09.05.2021 by a.kurka
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity arcCosFP is
	port(	nrst			: in std_logic;
			clk 			: in std_logic;
			ceacos     : in std_logic;-- startimpuls afkt
			ainp			:in std_logic_vector(31 downto 0);-- input afkt FP  format
			acos			:OUT std_logic_vector(31 downto 0):=X"00000000"-- output afkt FP  format
			);
end arcCosFP;

architecture Behavioral of arcCosFP is

COMPONENT afkt is
	generic(	P0:std_logic_vector(31 downto 0):=X"00000000";
				P1:std_logic_vector(31 downto 0):=X"00000000";
				P2:std_logic_vector(31 downto 0):=X"00000000";
				Q0:std_logic_vector(31 downto 0):=X"00000000";
				Q1:std_logic_vector(31 downto 0):=X"00000000";
				Q2:std_logic_vector(31 downto 0):=X"00000000"
				);
	port(	nrst			: in std_logic;
			clk 			: in std_logic;
			ceafkt     : in std_logic;-- startimpuls afkt
			Xinp			:in std_logic_vector(31 downto 0);-- input afkt FP  format
			aout		:OUT std_logic_vector(31 downto 0)-- output afkt FP  format
			);
END COMPONENT;
-----------------------------------------
COMPONENT subFP IS
	port (
	a: IN std_logic_VECTOR(31 downto 0);
	b: IN std_logic_VECTOR(31 downto 0);
	clk: IN std_logic;
	ce: IN std_logic;
	result: OUT std_logic_VECTOR(31 downto 0));
END COMPONENT;
-----------------------------------------------------
COMPONENT sqrtFP IS
	port (
	a: IN std_logic_VECTOR(31 downto 0);
	clk: IN std_logic;
	ce: IN std_logic;
	result: OUT std_logic_VECTOR(31 downto 0));
END COMPONENT;

----------------------------------------------------
COMPONENT mulFP IS
	port (
	a: IN std_logic_VECTOR(31 downto 0);
	b: IN std_logic_VECTOR(31 downto 0);
	clk: IN std_logic;
	ce: IN std_logic;
	result: OUT std_logic_VECTOR(31 downto 0));
END COMPONENT;
------------------------------------
--If a greater then equal then true
COMPONENT compFP IS
	port (
	a: IN std_logic_VECTOR(31 downto 0);
	b: IN std_logic_VECTOR(31 downto 0);
	clk: IN std_logic;
	ce: IN std_logic;
	result: OUT std_logic_VECTOR(0 downto 0));
END COMPONENT;
--========================================================
CONSTANT PIdiv2 	:std_logic_vector(31 DOWNTO 0):=X"3FC90FDB";--1.57079632679 PI/2 in FP Format
CONSTANT C0 		:std_logic_vector(31 DOWNTO 0):=X"00000000";-- zahl 0 in FP format 32bit
CONSTANT C1 		:std_logic_vector(31 DOWNTO 0):=X"3F800000";-- zahl 1 in FP format 32bit
CONSTANT C2 		:std_logic_vector(31 DOWNTO 0):=X"40000000";-- zahl 2 in FP format 32bit
CONSTANT C05 		:std_logic_vector(31 DOWNTO 0):=X"3F000000";-- zahl 0.5 in FP format 32bit
--==================================================================
SIGNAL ce1	 	:std_logic:= '0';
SIGNAL ce2	 	:std_logic:= '0';
SIGNAL ce3	 	:std_logic:= '0';
SIGNAL ce4	 	:std_logic:= '0';
SIGNAL ce5	 	:std_logic:= '0';
SIGNAL C1minX  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL Xinp2  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL ainp05 	:std_logic_VECTOR(0 downto 0):=(OTHERS => '0');-- output Compare Input(X) <= 0.5
SIGNAL mul2mX  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL C2powX  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL ain  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL sqrt2m  :std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL aou  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL Xq05  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL Xk05  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL angl1  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL asinX  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL angl2  	:std_logic_VECTOR(31 downto 0):=X"00000000";
SIGNAL state :INTEGER RANGE 0 TO 15:= 0;
--==================================================================
begin
--------------------------------------------------------------
pacos :PROCESS (clk)
VARIABLE cntrclk : INTEGER RANGE 0 TO 127:= 0;
--variable state :INTEGER RANGE 0 TO 7:= 0;
BEGIN
	IF rising_edge(clk) THEN
		IF nrst = '0' THEN
			state <= 0;
			cntrclk := 0;
			
			--(OTHERS => '0');
			
		ELSE
			CASE state IS
				WHEN 0 =>
					IF ceacos = '1' THEN
						ce1 <= '1';-- start für 1-x, x`2, ComP0.5
						state <= 1;
					ELSE
						state <= 0;
					END IF;
				WHEN 1 => --- Ausführen 1-x,X`2,CompX	
						ce1 <= '0';
						ce2 <= '1';-- start für mul2mxX,2powX berechnen
						state <= 2;
				WHEN 2 => ---- mul2mX,2powX fertig
						ce2 <= '0';
						state <= 3;
				WHEN 3 =>
					IF ainp05 = "1" THEN
						ain <= C1minX;
					ELSE
						ain <= C2powX;
					END IF;
						cntrclk := 11;
						ce3 <= '1'; --Start für afkt und sqrt
						state <= 4;
				WHEN 4 => -- ausführung afkt
					IF cntrclk = 0 THEN -- dann afkt(x) fertig, sqrt sowieso
						IF ainp05 = "1" THEN
							Xq05 <= aou;
						ELSE
							Xk05 <= aou;
						END IF;
						ce4 <= '1';-- start für angl1,asinX
						state <= 5;--
					ELSE	
						ce3   <= '0';-- reset ce3
						cntrclk := cntrclk - 1;
						state <= 4;
					END IF;	
				WHEN 5 =>  -- angl1 ,asinX fertig
					ce4 <= '0';
					ce5 <= '1';-- start für angl2
					state <= 6;
				WHEN 6 =>
					ce5 <= '0'; --reset
					state <= 7;
				WHEN 7 =>
					IF ainp05 = "1" THEN
						acos <= angl1;
					ELSE
						acos <= angl2;
					end IF;
					state <= 0; --warten auf nächste Start
				WHEN OTHERS =>
					state <= 0;
			END CASE;
		END IF; -- if nrst/else
  END IF; -- clk
END PROCESS;--end pacos

--=======Implementation==================================

Cafkt:   afkt
		generic map(P0=>X"3f7ffffd",-- +0.99999984852024669 
						P1=>X"be8c8cb6",-- -0.27451104135987186
						P2=>X"00000000",-- +0.0	
						Q0=>X"3f800000",-- +1.0 
						Q1=>X"beb73881",-- -0.35785296234245088
						Q2=>X"3c36a182"-- +0.011146905255803363 
						)	 
		port map(nrst=>nrst,clk=>clk,ceafkt=>ce3,Xinp=>ain,aout=>aou);

---------------------------------------
cminX: 	subFP port map(a=>C1,b=>ainp,clk=>clk,ce=>ce1,result=>C1minX);
CmulX2: mulFP port map(a=>ainp,b=>ainp,clk=>clk,ce=>ce1,result=>Xinp2);	
Ccomp:	compFP port map(a=>ainp,b=>C05,clk=>clk,ce=>ce1,result=>ainp05);
-------- 
cmul2mX:  mulFP port map(a=>C1minX,b=>C2,clk=>clk,ce=>ce2,result=>mul2mX);
Cmul2p: 	mulFP port map(a=>Xinp2,b=>C2,clk=>clk,ce=>ce2,result=>C2powX);	
--------
csqrt2: sqrtFP port map(a=>mul2mX,clk=>clk,ce=>ce3,result=>sqrt2m);
------
Cmula1: mulFP port map(a=>sqrt2m,b=>xq05,clk=>clk,ce=>ce4,result=>angl1);
Cmula2: mulFP port map(a=>Xk05,b=>ainp,clk=>clk,ce=>ce4,result=>asinX);
------
csub5: 	subFP port map(a=>PIdiv2,b=>asinX,clk=>clk,ce=>ce5,result=>angl2);
---------------------------------------------------	
end Behavioral;