library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity testbnch is
end entity TESTBNCH;

architecture stimulus of TESTBNCH is
------------------------------------------------
COMPONENT arctanFP is
	port (nrst		: in std_logic;
			clk 		: in std_logic;
			ceatan     : in std_logic;-- startimpuls afkt
			Xinp			:in std_logic_vector(31 downto 0);-- input X FP FP  format
			Yinp			:in std_logic_vector(31 downto 0);-- input Y FP FP  format
			atanFPo		:OUT std_logic_vector(31 downto 0):=X"00000000"-- output Winkel(rad) in FP  format
			);
end COMPONENT;

--====================================================================
	constant sim_cyc: time := 10 ns; -- 10 ns=100 MHz = system clk,clk =100Mhz

--======================================================
    signal tb_nrst         : std_logic  := '0';
    signal tb_clk          : std_logic  := '0';
	 signal tb_ceatan        : std_logic  := '0';
    signal tb_Xinp          : std_logic_vector(31 downto 0) := (others => '0');  --input X FP FP  format
    signal tb_Yinp           : std_logic_vector(31 downto 0) := (others => '0'); --input Y FP FP  format
    signal tb_atanFPo           : std_logic_vector(31 downto 0) := (others => '0');  --output Winkel(rad) in FP  format
   
	
---===============================================================================================
begin
------------------------------------------------
UUT:arctanFP
    port map
    (
		 nrst     => tb_nrst,     -- : in  std_logic;
        clk     => tb_clk,      -- : in  std_logic;
		  ceatan  => tb_ceatan, -- startimpuls afkt
			Xinp	 => tb_Xinp,  -- input X FP FP  format
			Yinp	 => tb_Yinp,	-- input Y FP FP  format
			atanFPo => tb_atanFPo 	-- output Winkel(rad) in FP  format
			);
--====================================================================

-------------------------------------------------------------------
--==========================================================
----------CLK= 100 MHz-----------------------------
    CLK_1: process
    begin
       tb_clk <= '0';
       WAIT FOR (sim_cyc*2 - 1 ns);
		WHILE TRUE LOOP
			tb_clk <= NOT tb_clk;
        	wait for (sim_cyc);--simcyc*2/2
        END LOOP;    
    end process;

---------------------------------------------------------------
    stimulus: process
    begin
		  tb_nrst <= '0';
		  WAIT for 5 us;
		  tb_nrst <= '1';-- reseted 
		  -----------------------------------
		  -------45Grd = 0.785398163 -----
		  -------30Grd = 0.523598776 -----
		  -----------------------------------
		  --tb_Xinp <= X"3f800000";--1.0
		  tb_Xinp <= X"3f032916";-- 0.512345678
		  tb_Yinp <= X"3f032916";--0.512345678
		 --------------------------
		 tb_ceatan  <= '1'; -- startimpuls
		 WAIT FOR sim_cyc*2;
		 tb_ceatan  <= '0';
		 ---------------------------
			
        wait;
    end process;
	 


end architecture stimulus;