# ucf für xc7k325tBG676 ,27.03.2024 ,AK # nur relevante Signale aus der Entity #NET "clk2_in" TNM_NET = "MAIN_CLK"; #TIMESPEC "TS_MAIN_CLK" =PERIOD "MAIN_CLK"16.666 ns HIGH 50%; #NET "clk2_in" TNM_NET = "MAIN_CLK"; # # #PACE: Start of Constraints generated by PACE #BANK 12================ ############################################################## #################################### ###NET "SYSCLK_P" TNM_NET = TNM_sys_clk; ###TIMESPEC "TS_sysclk" = PERIOD "TNM_sys_clk" 5 ns; # NET "CLKIN_P" TNM_NET = TNM_clk_ref; # TIMESPEC "TS_clkin" = PERIOD "TNM_clkin" 10 ns ; #NET "Clk" TNM_NET = TNM_sys_clk; #TIMESPEC "TS_sysclk" = PERIOD "TNM_sys_clk" 10 ns; ############## NET - IOSTANDARD ################## NET nrst LOC = E11 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L14P_T2_SRCC_16 NET ceatan LOC = Y26 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L24N_T3_32 #NET outvalid LOC = Y25 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_25_VRP_32 #------------------------------------------------------------------------ #NET LOC = A12 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L24N_T3_16 # DB1 #NET LOC = J14 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_25_16 # DB0 #NET LOC = V11 | IOSTANDARD #BANK33IO_L1P_T0_33 #NET LOC = V8 | IOSTANDARD = LVCMOS18 ; #BANK 33 IO_L2P_T0_33, PSRAM PCLK #--------BANK 12: 3V3V----Master Interface / Prit-Stecker ST1----------- NET XInp<0> LOC=Y20 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_0_VRN_32 mD0 NET XInp<1> LOC=AF22 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L1P_T0_32 mD1 NET XInp<2> LOC=AE22 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L1N_T0_32 mD2 NET XInp<3> LOC=AE25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L2P_T0_32 mD3 NET XInp<4> LOC=AD25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L2N_T0_32 mD4 NET XInp<5> LOC=AF23 |IOSTANDARD= LVCMOS33 ; #BANK 12 IO_L3P_T0_DQS_32 mD5 NET XInp<6> LOC=AE23 |IOSTANDARD= LVCMOS33 ; #BANK 12 IO_L3N_T0_DQS_32 mD6 NET XInp<7> LOC=AE26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD7 #------------bANK 13--------------------------------------------- NET XInp<8> LOC=N16 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD8 NET XInp<9> LOC=K25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD9 NET XInp<10> LOC=K26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD10 NET XInp<11> LOC=R26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD11 NET XInp<12> LOC=P26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD12 NET XInp<13> LOC=M25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD13 NET XInp<14> LOC=L25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD14 NET XInp<15> LOC=P24 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD15 NET XInp<16> LOC=N24 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD16 NET XInp<17> LOC=N26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD17 NET XInp<18> LOC=M26 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD18 NET XInp<19> LOC=R25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD19 NET XInp<20> LOC=P25 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD20 NET XInp<21> LOC=N19 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD21 NET XInp<22> LOC=M20 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD22 NET XInp<23> LOC=M24 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD23 NET XInp<24> LOC=L24 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD24 NET XInp<25> LOC=P19 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD25 NET XInp<26> LOC=P20 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD26 NET XInp<27> LOC=M21 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD27 NET XInp<28> LOC=M22 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD28 NET XInp<29> LOC=P23 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD29 NET XInp<30> LOC=N23 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD30 NET XInp<31> LOC=N21 |IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L4P_T0_32 mD31 #-------------------------------------------------------- NET YInp<0> LOC=AD26 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L1P_T0_32 mA0 NET YInp<1> LOC=AF25 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L1N_T0_32 mA1 NET YInp<2> LOC=AF24 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L2P_T0_32 mA2 NET YInp<3> LOC=AE21 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L2N_T0_32 mA3 NET YInp<4> LOC=AC22 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L3P_T0_32 mA4 NET YInp<5> LOC=AD24 |IOSTANDARD = LVCMOS33 ; #BANK 32 IO_L3N_T0_32 mA5 NET YInp<6> LOC = Y21 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L13P_T2_MRCC_32 NET YInp<7> LOC = W20 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L13N_T2_MRCC_32 NET YInp<8> LOC = AC24 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L20N_T3_32 NET YInp<9> LOC = AC23 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L21P_T3_DQS_32 NET YInp<10> LOC = AA22 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L21N_T3_DQS_32 NET YInp<11> LOC = Y22 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L22P_T3_32 NET YInp<12> LOC = AA24 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L22N_T3_32 NET YInp<13> LOC = Y23 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L23P_T3_32 NET YInp<14> LOC = AB24 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L23N_T3_32 NET YInp<15> LOC = AA23 | IOSTANDARD = LVCMOS33 ; #BANK 12 IO_L24P_T3_32 NET YInp<16> LOC= U22 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L1P_T0_12 #tst0 NET YInp<17> LOC= V22 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L1N_T0_12 #tst1 NET YInp<18> LOC= U24 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L2P_T0_12 #tst2 NET YInp<19> LOC= U25 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L2N_T0_12 #tst3 NET YInp<20> LOC= V23 |IOSTANDARD= LVCMOS33;#BANK12IO_L3P_T0_DQS_12 #tst4 NET YInp<21> LOC= V24 |IOSTANDARD= LVCMOS33;#BANK12IO_L3N_T0_DQS_12 #tst5 NET YInp<22> LOC= U26 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L4P_T0_12 #tst6 NET YInp<23> LOC= V26 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L4N_T0_12 #tst7 NET YInp<24> LOC = W25 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L5P_T0_12 #tst8 NET YInp<25> LOC = W26 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L5N_T0_12 #tst9 NET YInp<26> LOC = V21 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L6P_T0_12 #tst10 NET YInp<27> LOC= W21 |IOSTANDARD= LVCMOS33;#BANK12IO_L6N_T0_VREF_12 #tst11 NET YInp<28> LOC= AA25 |IOSTANDARD = LVCMOS33 ;#BANK 12 IO_L7P_T1_12 #tst12 NET YInp<29> LOC= AB25 |IOSTANDARD = LVCMOS33 ;#BANK 12 IO_L7N_T1_12 #tst13 NET YInp<30> LOC= W23 |IOSTANDARD = LVCMOS33 ;#BANK 12 IO_L8P_T1_12 #tst14 NET YInp<31> LOC= W24 |IOSTANDARD = LVCMOS33 ;#BANK 12 IO_L8N_T1_12 #tst15 #------------------------------------------- NET atanFPo<0> LOC = AD21 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L19P_T3_12 #P10 NET atanFPo<1> LOC = AC21 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L18N_T2_12 #P11 NET atanFPo<2> LOC = AB21 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L18P_T2_12 #P12 NET atanFPo<3> LOC = AB22 |IOSTANDARD= LVCMOS33 ;#BANK 12 IO_L17P_T2_12 #P13 NET atanFPo<4> LOC = R20 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L16N_T2_13 #I6E NET atanFPo<5> LOC = T22 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L17P_T2_13 #B6E NET atanFPo<6> LOC = T23 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L17N_T2_13 #A6E NET atanFPo<7> LOC = U19 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L18P_T2_13 #I5E NET atanFPo<8> LOC = U20 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L18N_T2_13 #B5E NET atanFPo<9> LOC = T18 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L19P_T3_13 #A5E NET atanFPo<10> LOC = T19 |IOSTANDARD= LVCMOS33;#BANK 13 IO_L19N_T3_VREF_13#I4E NET atanFPo<11> LOC = P16 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L20P_T3_13 #B4E NET atanFPo<12> LOC = N17 |IOSTANDARD = LVCMOS33 ; #BANK 13 IO_L20N_T3_13 #A4E NET atanFPo<13> LOC = R16 |IOSTANDARD= LVCMOS33;#BANK 13 IO_L21P_T3_DQS_13 #I3E NET atanFPo<14> LOC = R17 |IOSTANDARD= LVCMOS33;#BANK 13 IO_L21N_T3_DQS_13 #B3E NET atanFPo<15> LOC = N18 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L22P_T3_13 #A3E NET atanFPo<16> LOC = M19 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L22N_T3_13 #I2E NET atanFPo<17> LOC = U17 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L23P_T3_13 #B2E NET atanFPo<18> LOC = T17 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L23N_T3_13 #A2E NET atanFPo<19> LOC = R18 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L24P_T3_13 #I1E NET atanFPo<20> LOC = P18 |IOSTANDARD= LVCMOS33 ; #BANK 13 IO_L24N_T3_13 #B1E NET atanFPo<21> LOC = U16 |IOSTANDARD= LVCMOS33 ;#BANK 13 IO_25_13 #A1E NET atanFPo<22> LOC = J8 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_0_16 NET atanFPo<23> LOC = H9 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L1P_T0_16 NET atanFPo<24> LOC = H8 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L1N_T0_16 NET atanFPo<25> LOC = G10 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L2P_T0_16 NET atanFPo<26> LOC = G9 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L2N_T0_16 NET atanFPo<27> LOC = J13 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L3P_T0_DQS_16 NET atanFPo<28> LOC = H13 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L3N_T0_DQS_16 NET atanFPo<29> LOC = J11 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L4P_T0_16 NET atanFPo<30> LOC = J10 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L4N_T0_16 NET atanFPo<31> LOC = H14 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L5P_T0_16 #---------------------------------------------------------------- #NET LOC = G14 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L5N_T0_16 #NET LOC = H12 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L6P_T0_16 #NET LOC = H11 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L6N_T0_VREF_16 #NET LOC = F9 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L7P_T1_16 #---------------------------------------------------------------<0> LOC = F8 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L7N_T1_16 # A1ER #NET <1> LOC = D9 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L8P_T1_16 # <2> LOC = D8 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L8N_T1_16 # A2ER #NET <3> LOC = A9 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L9P_T1_DQS_16 # A2EL #NET <4> LOC = A8 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L9N_T1_DQS_16 # A3ER #NET <5> LOC = C9 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L10P_T1_16 # A3EL #NET <6> LOC = B9 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L10N_T1_16 # A4ER #NET <7> LOC = G11 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L11P_T1_SRCC_16 # A4EL #NET <9> LOC = E10 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L12P_T1_MRCC_16 # A5EL #NET <10> LOC= D10 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L12N_T1_MRCC_16 # A6ER #NET <11> LOC= C12 |IOSTANDARD= LVCMOS33;#BANK 16 IO_L13P_T2_MRCC_16 # A6EL #NET <12> LOC = D11 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L14N_T2_SRCC_16 #NET <13> LOC = F14 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L15P_T2_DQS_16 #NET <14> LOC = F13 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L15N_T2_DQS_16 #NET <15> LOC = G12 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L16P_T2_16 #NET <16> LOC = F12 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L16N_T2_16 #NET <17> LOC = D14 | IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L17P_T2_16 #NET <18> LOC = D13 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L17N_T2_16 # AD7 #NET <19> LOC = E13 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L18P_T2_16 # AD6 #NET <20> LOC = E12 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L18N_T2_16 # AD6 #NET <21> LOC = C14 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L19P_T3_16 # AD4 #NET <22> LOC = C13 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L19N_T3_VREF_16 # AD3 #NET <23> LOC = B12 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L20P_T3_16 # AD3 #NET <24> LOC = B11 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L20N_T3_16 # AD1 #NET <25> LOC = B14 |IOSTANDARD = LVCMOS33 ; #BANK 16 IO_L21P_T3_DQS_16 # AD0 #NET <26> LOC = A14 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L21N_T3_DQS_16 # DB7 #NET <27> LOC = B10 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L22P_T3_16 # DB6 #NET <28> LOC = A10 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L22N_T3_16 # DB5 #NET <29> LOC = B15 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L23P_T3_16 # DB4 #NET <30> LOC = A15 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L23N_T3_16 # DB3 #NET <31> LOC = A13 |IOSTANDARD= LVCMOS33 ; #BANK 16 IO_L24P_T3_16 # DB2 #-------------------======================================================== NET CLK LOC= AA9 |IOSTANDARD= LVCMOS18; #Pad fct:IO_L11P_T1_SRCC_33 #----------------- #PACE: Start of PACE Area Constraints #PACE: Start of PACE Prohibit Constraints #PACE: End of Constraints generated by PACE;