Release 14.7 Map P.20131013 (nt) Xilinx Mapping Report File for Design 'arctanFP' Design Information ------------------ Command Line : map -intstyle ise -p xc7k325t-fbg676-3 -w -logic_opt off -ol high -t 1 -xt 0 -register_duplication off -r 4 -mt off -ir off -pr off -lc off -power off -o arctanFP_map.ncd arctanFP.ngd arctanFP.pcf Target Device : xc7k325t Target Package : fbg676 Target Speed : -3 Mapper Version : kintex7 -- $Revision: 1.55 $ Mapped Date : Wed Sep 11 10:38:51 2024 Design Summary -------------- Number of errors: 0 Number of warnings: 0 Slice Logic Utilization: Number of Slice Registers: 157 out of 407,600 1% Number used as Flip Flops: 157 Number used as Latches: 0 Number used as Latch-thrus: 0 Number used as AND/OR logics: 0 Number of Slice LUTs: 143 out of 203,800 1% Number used as logic: 115 out of 203,800 1% Number using O6 output only: 73 Number using O5 output only: 7 Number using O5 and O6: 35 Number used as ROM: 0 Number used as Memory: 24 out of 64,000 1% Number used as Dual Port RAM: 0 Number used as Single Port RAM: 0 Number used as Shift Register: 24 Number using O6 output only: 20 Number using O5 output only: 0 Number using O5 and O6: 4 Number used exclusively as route-thrus: 4 Number with same-slice register load: 4 Number with same-slice carry load: 0 Number with other load: 0 Slice Logic Distribution: Number of occupied Slices: 73 out of 50,950 1% Number of LUT Flip Flop pairs used: 171 Number with an unused Flip Flop: 24 out of 171 14% Number with an unused LUT: 28 out of 171 16% Number of fully used LUT-FF pairs: 119 out of 171 69% Number of unique control sets: 4 Number of slice register sites lost to control set restrictions: 15 out of 407,600 1% A LUT Flip Flop pair for this architecture represents one LUT paired with one Flip Flop within a slice. A control set is a unique combination of clock, reset, set, and enable signals for a registered element. The Slice Logic Distribution report is not meaningful if the design is over-mapped for a non-slice resource or if Placement fails. OVERMAPPING of BRAM resources should be ignored if the design is over-mapped for a non-BRAM resource or if placement fails. IO Utilization: Number of bonded IOBs: 99 out of 400 24% Number of LOCed IOBs: 99 out of 99 100% Specific Feature Utilization: Number of RAMB36E1/FIFO36E1s: 0 out of 445 0% Number of RAMB18E1/FIFO18E1s: 0 out of 890 0% Number of BUFG/BUFGCTRLs: 1 out of 32 3% Number used as BUFGs: 1 Number used as BUFGCTRLs: 0 Number of IDELAYE2/IDELAYE2_FINEDELAYs: 0 out of 500 0% Number of ILOGICE2/ILOGICE3/ISERDESE2s: 0 out of 500 0% Number of ODELAYE2/ODELAYE2_FINEDELAYs: 0 out of 150 0% Number of OLOGICE2/OLOGICE3/OSERDESE2s: 0 out of 500 0% Number of PHASER_IN/PHASER_IN_PHYs: 0 out of 40 0% Number of PHASER_OUT/PHASER_OUT_PHYs: 0 out of 40 0% Number of BSCANs: 0 out of 4 0% Number of BUFHCEs: 0 out of 168 0% Number of BUFRs: 0 out of 40 0% Number of CAPTUREs: 0 out of 1 0% Number of DNA_PORTs: 0 out of 1 0% Number of DSP48E1s: 2 out of 840 1% Number of EFUSE_USRs: 0 out of 1 0% Number of FRAME_ECCs: 0 out of 1 0% Number of GTXE2_CHANNELs: 0 out of 16 0% Number of GTXE2_COMMONs: 0 out of 4 0% Number of IBUFDS_GTE2s: 0 out of 8 0% Number of ICAPs: 0 out of 2 0% Number of IDELAYCTRLs: 0 out of 10 0% Number of IN_FIFOs: 0 out of 40 0% Number of MMCME2_ADVs: 0 out of 10 0% Number of OUT_FIFOs: 0 out of 40 0% Number of PCIE_2_1s: 0 out of 1 0% Number of PHASER_REFs: 0 out of 10 0% Number of PHY_CONTROLs: 0 out of 10 0% Number of PLLE2_ADVs: 0 out of 10 0% Number of STARTUPs: 0 out of 1 0% Number of XADCs: 0 out of 1 0% Average Fanout of Non-Clock Nets: 2.17 Peak Memory Usage: 859 MB Total REAL time to MAP completion: 35 secs Total CPU time to MAP completion: 35 secs Table of Contents ----------------- Section 1 - Errors Section 2 - Warnings Section 3 - Informational Section 4 - Removed Logic Summary Section 5 - Removed Logic Section 6 - IOB Properties Section 7 - RPMs Section 8 - Guide Report Section 9 - Area Group and Partition Summary Section 10 - Timing Report Section 11 - Configuration String Information Section 12 - Control Set Information Section 13 - Utilization by Hierarchy Section 1 - Errors ------------------ Section 2 - Warnings -------------------- WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases. Section 3 - Informational ------------------------- INFO:Security:56 - Part 'xc7k325t' is not a WebPack part. INFO:LIT:243 - Logical network cfuncmul/sig000000de has no load. INFO:LIT:395 - The above info message is repeated 16 more times for the following (max. 5 shown): cfuncmul/sig000000dd, cfuncmul/sig000000dc, cfuncmul/sig000000db, cfuncmul/sig000000da, cfuncmul/sig000000d9 To see the details of these info messages, please use the -detail switch. INFO:LIT:244 - All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. INFO:Pack:1716 - Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) INFO:Pack:1720 - Initializing voltage to 0.970 Volts. (default - Range: 0.970 to 1.030 Volts) INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report (.mrp). INFO:Pack:1650 - Map created a placed design. Section 4 - Removed Logic Summary --------------------------------- 1 block(s) removed 3 block(s) optimized away 17 signal(s) removed Section 5 - Removed Logic ------------------------- The trimmed logic report below shows the logic removed from your design due to sourceless or loadless signals, and VCC or ground connections. If the removal of a signal or symbol results in the subsequent removal of an additional signal or symbol, the message explaining that second removal will be indented. This indentation will be repeated as a chain of related logic is removed. To quickly locate the original cause for the removal of a chain of logic, look above the place where that logic is listed in the trimming report, then locate the lines that are least indented (begin at the leftmost edge). Loadless block "cfuncmul/blk00000095" (XOR) removed. The signal "cfuncmul/sig000000de" is sourceless and has been removed. The signal "cfuncmul/sig000000dd" is sourceless and has been removed. The signal "cfuncmul/sig000000dc" is sourceless and has been removed. The signal "cfuncmul/sig000000db" is sourceless and has been removed. The signal "cfuncmul/sig000000da" is sourceless and has been removed. The signal "cfuncmul/sig000000d9" is sourceless and has been removed. The signal "cfuncmul/sig000000d8" is sourceless and has been removed. The signal "cfuncmul/sig000000d7" is sourceless and has been removed. The signal "cfuncmul/sig000000d6" is sourceless and has been removed. The signal "cfuncmul/sig000000d5" is sourceless and has been removed. The signal "cfuncmul/sig000000d4" is sourceless and has been removed. The signal "cfuncmul/sig000000d3" is sourceless and has been removed. The signal "cfuncmul/sig000000b8" is sourceless and has been removed. The signal "cfuncmul/sig000000b7" is sourceless and has been removed. The signal "cfuncmul/sig000000b6" is sourceless and has been removed. The signal "cfuncmul/sig000000b5" is sourceless and has been removed. The signal "cfuncmul/sig000000b4" is sourceless and has been removed. Optimized Block(s): TYPE BLOCK VCC cfuncmul/blk00000001 GND cfuncmul/blk00000002 GND cfuncmul/blk00000048/blk00000049 To enable printing of redundant blocks removed and signals merged, set the detailed map report option and rerun map. Section 6 - IOB Properties -------------------------- +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | | | | | | Term | Strength | Rate | | | Delay | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ | Xinp<0> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<1> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<2> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<3> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<4> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<5> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<6> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<7> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<8> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<9> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<10> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<11> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<12> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<13> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<14> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<15> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<16> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<17> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<18> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<19> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<20> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<21> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<22> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<23> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<24> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<25> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<26> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<27> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<28> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<29> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<30> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Xinp<31> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<0> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<1> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<2> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<3> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<4> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<5> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<6> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<7> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<8> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<9> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<10> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<11> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<12> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<13> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<14> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<15> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<16> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<17> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<18> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<19> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<20> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<21> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<22> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<23> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<24> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<25> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<26> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<27> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<28> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<29> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<30> | IOB33 | INPUT | LVCMOS33 | | | | | | | | Yinp<31> | IOB33 | INPUT | LVCMOS33 | | | | | | | | atanFPo<0> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<1> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<2> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<3> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<4> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<5> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<6> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<7> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<8> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<9> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<10> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<11> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<12> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<13> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<14> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<15> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<16> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<17> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<18> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<19> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<20> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<21> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<22> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<23> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<24> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<25> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<26> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<27> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<28> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<29> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<30> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | atanFPo<31> | IOB33 | OUTPUT | LVCMOS33 | | 12 | SLOW | | | | | ceatan | IOB33 | INPUT | LVCMOS33 | | | | | | | | clk | IOB | INPUT | LVCMOS18 | | | | | | | | nrst | IOB33 | INPUT | LVCMOS33 | | | | | | | +---------------------------------------------------------------------------------------------------------------------------------------------------------+ Section 7 - RPMs ---------------- Section 8 - Guide Report ------------------------ Guide not run on this design. Section 9 - Area Group and Partition Summary -------------------------------------------- Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- Area Group Information ---------------------- No area groups were found in this design. ---------------------- Section 10 - Timing Report -------------------------- A logic-level (pre-route) timing report can be generated by using Xilinx static timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the mapped NCD and PCF files. Please note that this timing report will be generated using estimated delay information. For accurate numbers, please generate a timing report with the post Place and Route NCD file. For more information about the Timing Analyzer, consult the Xilinx Timing Analyzer Reference Manual; for more information about TRCE, consult the Xilinx Command Line Tools User Guide "TRACE" chapter. Section 11 - Configuration String Details ----------------------------------------- Use the "-detail" map option to print out Configuration Strings Section 12 - Control Set Information ------------------------------------ Use the "-detail" map option to print out Control Set Information. Section 13 - Utilization by Hierarchy ------------------------------------- Use the "-detail" map option to print out the Utilization by Hierarchy section.