Place & Route TRACE Report
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version ispLever_v8.0_PROD_Build (41)
Mon Jun 21 13:06:41 2010
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -sethld -o checkpnt.twr transceiver_test_v3.ncd transceiver_test_v3.prf
Design file: transceiver_test_v3.ncd
Preference file: transceiver_test_v3.prf
Device,speed: LCMXO2280C,5
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "TXCLK" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz (0 errors) 1 item scored, 0 timing errors detected.
FREQUENCY PORT "VCXO_24R" 25.000000 MHz (0 errors) 72 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 1.188ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RECEIVER/BUFFER_MODUL/SHIFT_BUFFER/shft_cntl/fill_cnt_i_1 (from test_receiver_i -)
Destination: FF Data in RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/cnt_en_i (to txc_i +)
Delay: 2.714ns (35.7% logic, 64.3% route), 3 logic levels.
Constraint Details:
2.714ns physical path delay RECEIVER/BUFFER_MODUL/SHIFT_BUFFER/shft_cntl/SLICE_21 to RECEIVER/BUFFER_MODUL/SLICE_57 meets
20.000ns delay constraint less
15.969ns skew and
0.129ns DIN_SET requirement (totaling 3.902ns) by 1.188ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.438 R10C4A.CLK to R10C4A.Q1 RECEIVER/BUFFER_MODUL/SHIFT_BUFFER/shft_cntl/SLICE_21 (from test_receiver_i)
ROUTE 2 0.738 R10C4A.Q1 to R10C4D.B1 RECEIVER/BUFFER_MODUL/SHIFT_BUFFER/shft_cntl/fill_cnt_i_1
CTOF_DEL --- 0.265 R10C4D.B1 to R10C4D.F1 SLICE_108
ROUTE 1 0.964 R10C4D.F1 to R13C4A.C0 RECEIVER/BUFFER_MODUL/SHIFT_BUFFER/shft_cntl/wr_to_ebr_i3lto3_0
CTOF_DEL --- 0.265 R13C4A.C0 to R13C4A.F0 RECEIVER/BUFFER_MODUL/SLICE_57
ROUTE 5 0.044 R13C4A.F0 to R13C4A.DI0 RECEIVER/BUFFER_MODUL/WR_TO_EBR_0_a2_0_a2 (to txc_i)
--------
2.714 (35.7% logic, 64.3% route), 3 logic levels.
Clock Skew Details:
Source Clock Path::
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.754 60.PAD to 60.PADDI TXCLK
ROUTE 73 3.523 60.PADDI to R7C4B.CLK txc_i
REG_DEL --- 0.438 R7C4B.CLK to R7C4B.Q0 TRANSMITTER/SLICE_153
ROUTE 6 1.225 R7C4B.Q0 to R8C3C.C0 TRANSMITTER/sbclk_i
CTOF_DEL --- 0.265 R8C3C.C0 to R8C3C.F0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175
ROUTE 4 1.693 R8C3C.F0 to EBR_R5C1.CLKR TRANSMITTER/BUFFER_MODUL/N_426
C2Q_DEL --- 2.265 EBR_R5C1.CLKR to EBR_R5C1.DO4 TRANSMITTER/BUFFER_MODUL/EBR_BUFFER/RAM_A/ram_48x16_0_0_0
ROUTE 1 1.523 EBR_R5C1.DO4 to R8C2A.A0 TRANSMITTER/BUFFER_MODUL/q_a_4
CTOOFX_DEL --- 0.451 R8C2A.A0 to R8C2A.OFX0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/D_OUT_1_i_m2_0/SLICE_131
ROUTE 1 1.031 R8C2A.OFX0 to R8C4B.B1 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_432
CTOF_DEL --- 0.265 R8C4B.B1 to R8C4B.F1 TRANSMITTER/SLICE_139
ROUTE 1 0.355 R8C4B.F1 to R8C4B.C0 TRANSMITTER/N_165_i
CTOF_DEL --- 0.265 R8C4B.C0 to R8C4B.F0 TRANSMITTER/SLICE_139
ROUTE 5 1.741 R8C4B.F0 to R8C7D.A1 eth_channel_i_0
CTOF_DEL --- 0.265 R8C7D.A1 to R8C7D.F1 RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174
ROUTE 1 1.650 R8C7D.F1 to R8C6D.CLK RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i
LTCH_DEL --- 0.531 R8C6D.CLK to R8C6D.Q0 SLICE_111
ROUTE 37 0.816 R8C6D.Q0 to R10C6D.D0 t_pin_i
CTOF_DEL --- 0.265 R10C6D.D0 to R10C6D.F0 RECEIVER/SLICE_134
ROUTE 19 0.925 R10C6D.F0 to R10C4A.CLK test_receiver_i
--------
20.246 (28.5% logic, 71.5% route), 10 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.754 60.PAD to 60.PADDI TXCLK
ROUTE 73 3.523 60.PADDI to R13C4A.CLK txc_i
--------
4.277 (17.6% logic, 82.4% route), 1 logic levels.
Report: 26.579MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 10308.189ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (from TRANSMITTER/swclk_i +)
Destination: FF Data in TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (to TRANSMITTER/swclk_i +)
Delay: 0.961ns (41.6% logic, 58.4% route), 1 logic levels.
Constraint Details:
0.961ns physical path delay TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 to TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 meets
10309.278ns delay constraint less
0.000ns skew and
0.128ns M_SET requirement (totaling 10309.150ns) by 10308.189ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.400 R6C4A.CLK to R6C4A.Q0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 (from TRANSMITTER/swclk_i)
ROUTE 47 0.561 R6C4A.Q0 to R6C4A.M0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (to TRANSMITTER/swclk_i)
--------
0.961 (41.6% logic, 58.4% route), 1 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
1.133ns R5C5C.Q0 to R6C4A.CLK
Destination Clock :
Delay Connection
1.133ns R5C5C.Q0 to R6C4A.CLK
Report: 918.274MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
72 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 36.480ns
The internal maximum frequency of the following component is 284.091 MHz
Logical Details: Cell type Pin name Component name
Destination: DP8KB CLKA RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/DP_RAM/dpram_48x16_0_0_0
Delay: 3.520ns -- based on Minimum Pulse Width
Passed: The following path meets requirements by 36.701ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RECEIVER/READ_OUT/adr_cnt_i_3 (from RECEIVER/READ_OUT/un2_rdck_en_i_i_i +)
Destination: DP8KB Port RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/DP_RAM/dpram_48x16_0_0_0(ASIC) (to RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_412 +)
Delay: 3.710ns (21.5% logic, 78.5% route), 2 logic levels.
Constraint Details:
3.710ns physical path delay RECEIVER/READ_OUT/SLICE_76 to RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/DP_RAM/dpram_48x16_0_0_0 meets
40.000ns delay constraint less
-0.104ns skew and
-0.307ns ADDR_SET requirement (totaling 40.411ns) by 36.701ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
LTCH_DEL --- 0.531 R14C4A.CLK to R14C4A.Q0 RECEIVER/READ_OUT/SLICE_76 (from RECEIVER/READ_OUT/un2_rdck_en_i_i_i)
ROUTE 2 1.622 R14C4A.Q0 to R14C2A.C1 RECEIVER/rd_adr_i_3
CTOF_DEL --- 0.265 R14C2A.C1 to R14C2A.F1 RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_169
ROUTE 1 1.292 R14C2A.F1 to EBR_R13C1.ADA7 RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_417 (to RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_412)
--------
3.710 (21.5% logic, 78.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path::
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.754 87.PAD to 87.PADDI VCXO_24R
ROUTE 1 2.337 87.PADDI to R13C6A.CLK VCXO_24R_c
REG_DEL --- 0.400 R13C6A.CLK to R13C6A.Q0 RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78
ROUTE 5 1.142 R13C6A.Q0 to R14C5C.CLK RECEIVER/sync_cnt_i_1
REG_DEL --- 0.438 R14C5C.CLK to R14C5C.Q1 RECEIVER/READ_OUT/SLICE_64
ROUTE 11 1.172 R14C5C.Q1 to R15C4B.CLK RECEIVER/pre_cnt_i_0
REG_DEL --- 0.400 R15C4B.CLK to R15C4B.Q1 RECEIVER/READ_OUT/SLICE_6
ROUTE 7 0.836 R15C4B.Q1 to R14C4B.B0 RECEIVER/counter_i_0_3
CTOF_DEL --- 0.265 R14C4B.B0 to R14C4B.F0 RECEIVER/SLICE_197
ROUTE 3 0.500 R14C4B.F0 to R14C4A.CLK RECEIVER/READ_OUT/un2_rdck_en_i_i_i
--------
8.244 (27.4% logic, 72.6% route), 5 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.754 87.PAD to 87.PADDI VCXO_24R
ROUTE 1 2.337 87.PADDI to R13C6A.CLK VCXO_24R_c
REG_DEL --- 0.400 R13C6A.CLK to R13C6A.Q0 RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78
ROUTE 5 1.142 R13C6A.Q0 to R14C5C.CLK RECEIVER/sync_cnt_i_1
REG_DEL --- 0.438 R14C5C.CLK to R14C5C.Q1 RECEIVER/READ_OUT/SLICE_64
ROUTE 11 1.562 R14C5C.Q1 to R14C3C.D1 RECEIVER/pre_cnt_i_0
CTOF_DEL --- 0.265 R14C3C.D1 to R14C3C.F1 RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_172
ROUTE 2 1.450 R14C3C.F1 to EBR_R13C1.CLKA RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_412
--------
8.348 (22.2% logic, 77.8% route), 4 logic levels.
Report: 284.091MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "TXCLK" 25.000000 MHz ; | 25.000 MHz| 26.579 MHz| 3
| | |
FREQUENCY NET "TRANSMITTER/swclk_i" | | |
0.097000 MHz ; | 0.097 MHz| 918.274 MHz| 1
| | |
FREQUENCY PORT "VCXO_24R" 25.000000 MHz | | |
; | 25.000 MHz| 284.091 MHz| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 19 clocks:
Clock Domain: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_412 Source: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_172.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 2
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_413 Source: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_172.F0 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 2
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/pre_cnt_i_inferred_clock_6 Source: RECEIVER/READ_OUT/SLICE_1.Q0 Loads: 3
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Data transfers from:
Clock Domain: t_pin_i Source: SLICE_111.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/sync_cnt_i_1 Source: RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78.Q0 Loads: 5
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Clock Domain: VCXO_24R_c Source: VCXO_24R.PAD Loads: 1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Clock Domain: txc_i Source: TXCLK.PAD Loads: 73
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 5
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 2
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/un1_counter_i_reset10 Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_159.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 4
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 2
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 20
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 20
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1 Loads: 11
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0 Loads: 4
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0 Loads: 3
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: t_pin_i Source: SLICE_111.Q0 Loads: 37
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: RECEIVER/READ_OUT/pre_cnt_i_inferred_clock_6 Source: RECEIVER/READ_OUT/SLICE_1.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0 Loads: 19
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1 Loads: 1
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/un1_counter_i_reset10 Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_159.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0 Loads: 7
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 10
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0 Loads: 3
Covered under: FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz ;
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0 Loads: 6
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 36
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 3
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 36
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 3
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 5939 paths, 32 nets, and 1287 connections (86.6% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version ispLever_v8.0_PROD_Build (41)
Mon Jun 21 13:06:41 2010
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2009 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -sethld -o checkpnt.twr transceiver_test_v3.ncd transceiver_test_v3.prf
Design file: transceiver_test_v3.ncd
Preference file: transceiver_test_v3.prf
Device,speed: LCMXO2280C,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY PORT "TXCLK" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz (0 errors) 1 item scored, 0 timing errors detected.
FREQUENCY PORT "VCXO_24R" 25.000000 MHz (0 errors) 72 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/wr_cnt_i_5 (from TRANSMITTER/sbclk_i +)
Destination: FF Data in TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/wr_adr_i_3 (to TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 +)
Delay: 0.777ns (25.7% logic, 74.3% route), 2 logic levels.
Constraint Details:
0.777ns physical path delay TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_34 to TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_109 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
-0.783ns skew requirement (totaling 0.775ns) by 0.002ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R9C5C.CLK to R9C5C.Q1 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_34 (from TRANSMITTER/sbclk_i)
ROUTE 4 0.577 R9C5C.Q1 to R9C4C.A0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/wr_cnt_i_5
CTOF_DEL --- 0.074 R9C4C.A0 to R9C4C.F0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_109
ROUTE 1 0.000 R9C4C.F0 to R9C4C.DI0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_55_i (to TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0)
--------
0.777 (25.7% logic, 74.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path::
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.259 60.PAD to 60.PADDI TXCLK
ROUTE 73 1.215 60.PADDI to R7C4B.CLK txc_i
REG_DEL --- 0.150 R7C4B.CLK to R7C4B.Q0 TRANSMITTER/SLICE_153
ROUTE 6 0.391 R7C4B.Q0 to R9C5C.CLK TRANSMITTER/sbclk_i
--------
2.015 (20.3% logic, 79.7% route), 2 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.259 60.PAD to 60.PADDI TXCLK
ROUTE 73 1.215 60.PADDI to R7C4B.CLK txc_i
REG_DEL --- 0.150 R7C4B.CLK to R7C4B.Q0 TRANSMITTER/SLICE_153
ROUTE 6 0.391 R7C4B.Q0 to R9C5D.CLK TRANSMITTER/sbclk_i
REG_DEL --- 0.137 R9C5D.CLK to R9C5D.Q0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_33
ROUTE 7 0.377 R9C5D.Q0 to R9C4D.B0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/wr_cnt_i_6
CTOF_DEL --- 0.091 R9C4D.B0 to R9C4D.F0 TRANSMITTER/SLICE_196
ROUTE 4 0.178 R9C4D.F0 to R9C4C.CLK TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0
--------
2.798 (22.8% logic, 77.2% route), 4 logic levels.
================================================================================
Preference: FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz ;
1 item scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.307ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (from TRANSMITTER/swclk_i +)
Destination: FF Data in TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (to TRANSMITTER/swclk_i +)
Delay: 0.290ns (43.4% logic, 56.6% route), 1 logic levels.
Constraint Details:
0.290ns physical path delay TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 to TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 meets
-0.017ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.017ns) by 0.307ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R6C4A.CLK to R6C4A.Q0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_179 (from TRANSMITTER/swclk_i)
ROUTE 47 0.164 R6C4A.Q0 to R6C4A.M0 TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/ramsw_i (to TRANSMITTER/swclk_i)
--------
0.290 (43.4% logic, 56.6% route), 1 logic levels.
Clock Skew Details:
Source Clock:
Delay Connection
0.391ns R5C5C.Q0 to R6C4A.CLK
Destination Clock:
Delay Connection
0.391ns R5C5C.Q0 to R6C4A.CLK
================================================================================
Preference: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
72 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.009ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q RECEIVER/READ_OUT/counter_i_5 (from RECEIVER/pre_cnt_i_0 +)
Destination: FF Data in RECEIVER/READ_OUT/adr_cnt_i_4 (to RECEIVER/READ_OUT/un2_rdck_en_i_i_i +)
Delay: 0.689ns (29.0% logic, 71.0% route), 2 logic levels.
Constraint Details:
0.689ns physical path delay RECEIVER/READ_OUT/SLICE_5 to RECEIVER/READ_OUT/SLICE_76 meets
-0.008ns DIN_HLD and
0.000ns delay constraint less
-0.688ns skew requirement (totaling 0.680ns) by 0.009ns
Physical Path Details:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.126 R15C4C.CLK to R15C4C.Q1 RECEIVER/READ_OUT/SLICE_5 (from RECEIVER/pre_cnt_i_0)
ROUTE 4 0.489 R15C4C.Q1 to R14C4A.A1 RECEIVER/READ_OUT/counter_i_5
CTOF_DEL --- 0.074 R14C4A.A1 to R14C4A.F1 RECEIVER/READ_OUT/SLICE_76
ROUTE 1 0.000 R14C4A.F1 to R14C4A.DI1 RECEIVER/READ_OUT/N_406_i_i (to RECEIVER/READ_OUT/un2_rdck_en_i_i_i)
--------
0.689 (29.0% logic, 71.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path::
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.259 87.PAD to 87.PADDI VCXO_24R
ROUTE 1 0.805 87.PADDI to R13C6A.CLK VCXO_24R_c
REG_DEL --- 0.137 R13C6A.CLK to R13C6A.Q0 RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78
ROUTE 5 0.394 R13C6A.Q0 to R14C5C.CLK RECEIVER/sync_cnt_i_1
REG_DEL --- 0.150 R14C5C.CLK to R14C5C.Q1 RECEIVER/READ_OUT/SLICE_64
ROUTE 11 0.404 R14C5C.Q1 to R15C4C.CLK RECEIVER/pre_cnt_i_0
--------
2.149 (25.4% logic, 74.6% route), 3 logic levels.
Destination Clock Path:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.259 87.PAD to 87.PADDI VCXO_24R
ROUTE 1 0.805 87.PADDI to R13C6A.CLK VCXO_24R_c
REG_DEL --- 0.137 R13C6A.CLK to R13C6A.Q0 RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78
ROUTE 5 0.394 R13C6A.Q0 to R14C5C.CLK RECEIVER/sync_cnt_i_1
REG_DEL --- 0.150 R14C5C.CLK to R14C5C.Q1 RECEIVER/READ_OUT/SLICE_64
ROUTE 11 0.404 R14C5C.Q1 to R15C4B.CLK RECEIVER/pre_cnt_i_0
REG_DEL --- 0.137 R15C4B.CLK to R15C4B.Q1 RECEIVER/READ_OUT/SLICE_6
ROUTE 7 0.288 R15C4B.Q1 to R14C4B.B0 RECEIVER/counter_i_0_3
CTOF_DEL --- 0.091 R14C4B.B0 to R14C4B.F0 RECEIVER/SLICE_197
ROUTE 3 0.172 R14C4B.F0 to R14C4A.CLK RECEIVER/READ_OUT/un2_rdck_en_i_i_i
--------
2.837 (27.3% logic, 72.7% route), 5 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY PORT "TXCLK" 25.000000 MHz ; | -| -| 2
| | |
FREQUENCY NET "TRANSMITTER/swclk_i" | | |
0.097000 MHz ; | -| -| 1
| | |
FREQUENCY PORT "VCXO_24R" 25.000000 MHz | | |
; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 19 clocks:
Clock Domain: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_412 Source: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_172.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 2
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/N_413 Source: RECEIVER/BUFFER_MODUL/EBR_BUFFER_48x16/EBR_CONTROL/SLICE_172.F0 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 2
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/READ_OUT/pre_cnt_i_inferred_clock_6 Source: RECEIVER/READ_OUT/SLICE_1.Q0 Loads: 3
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Data transfers from:
Clock Domain: t_pin_i Source: SLICE_111.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/sync_cnt_i_1 Source: RECEIVER/PLL_MODUL/CLK_DIVIDER/SLICE_78.Q0 Loads: 5
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Clock Domain: VCXO_24R_c Source: VCXO_24R.PAD Loads: 1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Clock Domain: txc_i Source: TXCLK.PAD Loads: 73
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 5
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 2
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/un1_counter_i_reset10 Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_159.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 4
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 2
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 20
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 20
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1 Loads: 11
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ;
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1
Not reported because source and destination domains are unrelated.
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0
Not reported because source and destination domains are unrelated.
Clock Domain: RECEIVER/last_fillbit_i Source: RECEIVER/RECEIVE_MODUL/SLICE_194.F0 Loads: 4
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Clock Domain: RECEIVER/READ_OUT/un2_rdck_en_i_i_i Source: RECEIVER/SLICE_197.F0 Loads: 3
No transfer within this clock domain is found
Data transfers from:
Clock Domain: RECEIVER/pre_cnt_i_0 Source: RECEIVER/READ_OUT/SLICE_64.Q1
Covered under: FREQUENCY PORT "VCXO_24R" 25.000000 MHz ; Transfers: 6
Clock Domain: t_pin_i Source: SLICE_111.Q0 Loads: 37
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: RECEIVER/READ_OUT/pre_cnt_i_inferred_clock_6 Source: RECEIVER/READ_OUT/SLICE_1.Q0
Not reported because source and destination domains are unrelated.
Clock Domain: test_receiver_i Source: RECEIVER/SLICE_134.F0 Loads: 19
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Data transfers from:
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: RECEIVER/RECEIVE_MODUL/receiver_modul/N_33_i Source: RECEIVER/RECEIVE_MODUL/receiver_modul/SLICE_174.F1 Loads: 1
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/un1_counter_i_reset10 Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_159.F1 Loads: 2
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Clock Domain: TRANSMITTER/TRANSMITTER/transmitter_module/wclk_i_inferred_clock Source: TRANSMITTER/TRANSMITTER/transmitter_module/SLICE_96.Q0 Loads: 7
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 10
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0 Loads: 3
Covered under: FREQUENCY NET "TRANSMITTER/swclk_i" 0.097000 MHz ;
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0 Loads: 6
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ;
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_427_i Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F1 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 36
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 3
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: TRANSMITTER/BUFFER_MODUL/N_426 Source: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/SLICE_175.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: txc_i Source: TXCLK.PAD
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 36
Clock Domain: TRANSMITTER/swclk_i Source: TRANSMITTER/SLICE_106.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 1
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 3
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 6
Clock Domain: TRANSMITTER/BUFFER_MODUL/BUFFER_CONTROL/N_121_i_0 Source: TRANSMITTER/SLICE_196.F0 Loads: 4
No transfer within this clock domain is found
Data transfers from:
Clock Domain: TRANSMITTER/sbclk_i Source: TRANSMITTER/SLICE_153.Q0
Covered under: FREQUENCY PORT "TXCLK" 25.000000 MHz ; Transfers: 7
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 5942 paths, 32 nets, and 1287 connections (86.6% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
Generated from the file 'C:\ispTOOLS8_0_STRT\work\BoardRev2_0\Modultest_Trans_Rec_v3\transceiver_test_v3.twr'