1 | //I2C test
|
2 |
|
3 | #include "DSP280x_Device.h" // DSP280x Headerfile Include File
|
4 | #include "DSP280x_Examples.h" // DSP280x Examples Include File
|
5 |
|
6 | // Prototype statements for functions found within this file.
|
7 | void I2CA_Init(void);
|
8 | Uint16 I2C_Write(Uint16 slvaddr, int data, Uint16 length);
|
9 | Uint16 I2C_Read(Uint16 slvaddr, Uint16* data, Uint16 length);
|
10 |
|
11 | Uint16 Values[6];
|
12 |
|
13 | void main(void)
|
14 | {
|
15 | InitSysCtrl(); // Step 1. Initialize System Control:
|
16 | InitI2CGpio(); // Step 2. Initalize GPIO only for I2C functionality
|
17 | I2CA_Init(); // Step 4. Initialize all the Device Peripherals
|
18 |
|
19 | for(;;) // Application loop
|
20 | {
|
21 | I2C_Write(0x70,0x02,2);
|
22 | I2C_Read(0x71,Values,6);
|
23 | } // end of for(;;)
|
24 | } // end of main
|
25 |
|
26 |
|
27 | void I2CA_Init(void)
|
28 | {
|
29 | // I2caRegs.I2CSAR = 0x38; // Slave address - EEPROM control code
|
30 | I2caRegs.I2CPSC.all = 6; // Prescaler - need 7-12 Mhz on module clk for 60MHz CPU
|
31 | I2caRegs.I2CCLKL = 4200; // NOTE: must be non zero
|
32 | I2caRegs.I2CCLKH = 4200; // NOTE: must be non zero
|
33 | I2caRegs.I2CIER.all = 0x3E; // Enable SCD,XRDY,RRDY,ARDY,NACK interrupts
|
34 | // I2caRegs.I2CMDR.all = 0x0020; // Take I2C out of reset, Stop I2C when suspended
|
35 | // I2caRegs.I2CFFTX.all = 0x6000; // Enable FIFO mode and TXFIFO
|
36 | // I2caRegs.I2CFFRX.all = 0x2040; // Enable RXFIFO, clear RXFFINT,
|
37 | return;
|
38 | }
|
39 |
|
40 | Uint16 I2C_Write(Uint16 slvaddr, int data, Uint16 length)
|
41 | {
|
42 | Uint16 i;
|
43 | while (( I2caRegs.I2CSTR.bit.BB==1 )); //bus busy?
|
44 | if (I2caRegs.I2CSTR.bit.BB == 1)
|
45 | {
|
46 | return I2C_BUS_BUSY_ERROR;
|
47 | }
|
48 | I2caRegs.I2CMDR.all = 0; //disable I2C during config
|
49 | I2caRegs.I2CCNT = length; //number of bytes to be send
|
50 | I2caRegs.I2CSAR = slvaddr; //setup receiver addr
|
51 | // Mode settings
|
52 | I2caRegs.I2CMDR.bit.IRS=1; //I2C module enable
|
53 | I2caRegs.I2CMDR.bit.STT=1; //If master -> start condition generated
|
54 | I2caRegs.I2CMDR.bit.STP=1; //If master -> stop condition generated if data counter=0
|
55 | I2caRegs.I2CMDR.bit.TRX=1; //Transmitter mode
|
56 | I2caRegs.I2CMDR.bit.MST=1; //Master mode
|
57 | I2caRegs.I2CMDR.bit.FREE=1; //I2C module runs free
|
58 | I2caRegs.I2CMDR.bit.RM=1;
|
59 |
|
60 | /* Transmission*/
|
61 | for(i=0;i<length;i++)
|
62 | {
|
63 | while(!(I2caRegs.I2CSTR.bit.XRDY|I2caRegs.I2CSTR.bit.ARDY)); //wait for xdry flag before transmit data or ardy if NACK appears
|
64 | if (I2caRegs.I2CSTR.bit.NACK==1) //if NACK appears -> SCL=low, STP=0
|
65 | {
|
66 | I2caRegs.I2CMDR.all=0; //reset I2C -> SCL not held low
|
67 | }
|
68 | I2caRegs.I2CDXR = data;
|
69 | }
|
70 | }
|
71 |
|
72 | Uint16 I2C_Read(Uint16 slvaddr, Uint16* data, Uint16 length)
|
73 | {
|
74 | Uint16 i;
|
75 | while (( I2caRegs.I2CSTR.bit.BB==1 )); //bus busy?
|
76 | if (I2caRegs.I2CSTR.bit.BB == 1)
|
77 | {
|
78 | return I2C_BUS_BUSY_ERROR;
|
79 | }
|
80 | I2caRegs.I2CMDR.all = 0; //disable I2C during config
|
81 | I2caRegs.I2CCNT = length; //number of bytes to be send
|
82 | I2caRegs.I2CSAR = slvaddr; //setup receiver addr
|
83 | // Mode settings
|
84 | I2caRegs.I2CMDR.bit.IRS=1; //I2C module enable
|
85 | I2caRegs.I2CMDR.bit.STT=1; //If master -> start condition generated
|
86 | I2caRegs.I2CMDR.bit.STP=1; //If master -> stop condition generated if data counter = 0
|
87 | I2caRegs.I2CMDR.bit.MST=1; //Master mode
|
88 | I2caRegs.I2CMDR.bit.FREE=1; //I2C module runs free
|
89 | I2caRegs.I2CMDR.bit.NACKMOD=1;
|
90 |
|
91 | /* Reception */
|
92 | for(i=0;i<length;i++)
|
93 | {
|
94 | while(!(I2caRegs.I2CSTR.bit.XRDY|I2caRegs.I2CSTR.bit.ARDY)); //wait for xdry flag before transmit data or ardy if NACK appears
|
95 | if (I2caRegs.I2CSTR.bit.NACK==1) //if NACK appears -> SCL=low, STP=0
|
96 | {
|
97 | I2caRegs.I2CMDR.all=0; //reset I2C -> SCL not held low
|
98 | }
|
99 | while(I2caRegs.I2CSTR.bit.RRDY==1);
|
100 | data[i] = I2caRegs.I2CDRR ;
|
101 | }
|
102 | }
|
103 |
|
104 | //EOF
|