1 | static S1D_REGS init_values[] = \
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2 | { \
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3 | { 0x14, 0x00000000 }, /* Power Save Configuration Register(0x00000000) */ \
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4 | { 0x64, 0x28D70000 }, /* GPIO Status and Control Register */ \
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5 | { 0x04, 0x00000000 }, /* Memory Clock Configuration Register */ \
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6 | { 0x08, 0x00000032 }, /* Pixel Clock Configuration Register */ \
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7 | { 0x0C, 0x00000041 }, /* Panel Type and MOD Rate Register 0x61*/ \
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8 | { 0x10, 0x00000010 }, /* Display Settings Register */ \
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9 | { 0x20, 0x00000030 }, /* Horizontal Total Register */ \
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10 | { 0x24, 0x00000027 }, /* Horizontal Display Period Register */ \
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11 | { 0x28, 0x0000000F }, /* Horizontal Display Period Start Position Register */ \
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12 | { 0x2C, 0x00870156 }, /* FPLINE Register */ \
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13 | { 0x30, 0x00000103 }, /* Vertical Total Register */ \
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14 | { 0x34, 0x000000EF }, /* Vertical Display Period Register */ \
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15 | { 0x38, 0x00000013 }, /* Vertical Display Period Start Position Register */ \
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16 | { 0x3C, 0x00800000 }, /* FPFRAME Register */ \
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17 | { 0x40, 0x00000000 }, /* Main Window Display Start Address Register */ \
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18 | { 0x44, 0x000000A0 }, /* Main Window Line Address Offset Register */ \
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19 | { 0x50, 0x00000000 }, /* PIP+ Window Display Start Address Register */ \
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20 | { 0x54, 0x000000A0 }, /* PIP+ Window Line Address Offset Register */ \
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21 | { 0x58, 0x00000000 }, /* PIP+ Window X Positions Register */ \
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22 | { 0x5C, 0x00000000 }, /* PIP+ Window Y Positions Register */ \
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23 | { 0x60, 0x00000000 }, /* Special Purpose Register */ \
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24 | { 0x70, 0x00000000 }, /* PWM Clock Configuration Register */ \
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25 | { 0x74, 0x00000000 }, /* PWMOUT Duty Cycle Register */ \
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26 | { 0x80, 0x00000000 }, /* Scratch Pad A Register */ \
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27 | { 0x84, 0x00000000 }, /* Scratch Pad B Register */ \
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28 | { 0x88, 0x00000000 }, /* Scratch Pad C Register */ \
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29 | { S1D_REGDELAYON, 0x00000032 }, /* LCD Panel Power On Delay (in ms) */ \
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30 | { 0x64, 0x28D70001 }, /* GPIO Status and Control Register */ \
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31 | { 0x14, 0x00000000 } /* Power Save Configuration Register */ \
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32 | };
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