1 | /////Master
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2 | #include "p18F4550.h"
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3 | #include <stdio.h>
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4 | #include <delays.h>
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5 | #include "Spi_Init.h"
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6 | #include "PortConfiguration.h"
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7 | int u08LSend_Data=0x75;
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8 | void SPI_Init_Master(void)
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9 | {
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10 | SSPSTATbits.SMP=0 ; //1= Input data sampled at end of data output time
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11 | //0= Input data sampled at middle of data output time
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12 |
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13 | SSPSTATbits.CKE=1 ; //1= Transmit occurs on transition from active to Idle clock state
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14 | //0= transmit occurs on transition from Idle to active clock state
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15 |
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16 | SSPCON1bits.WCOL=0 ; //1= The SSPBUF register is written while it is still transmitting the previous word (must be clear in Software)
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17 | //0= No collision
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18 |
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19 | SSPCON1bits.SSPEN= 1; //1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
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20 | //0= Disables serial port and configures these pins as I/O port pins
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21 |
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22 | SSPCON1bits.CKP=1; //1= Idle state for clock is a high level
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23 | //0= Idle state for clock is a low level
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24 | //SSPM3:SSPM0: Master sychronous Serial Port Mode Select bits
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25 | SSPCON1bits.SSPM3= 0; //0101= SPI Slave mode, clock =SCK pin, SS pin control disabled, ss can be used as I/O pin
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26 | SSPCON1bits.SSPM2= 0; //0100= SPI slave mode, clock =SCK pin, SS pin control enabled
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27 | SSPCON1bits.SSPM1= 0; //0011= SPI Master mode, clock = TMR2 output/2
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28 | SSPCON1bits.SSPM0= 1; //0010= SPI Master mode, clock = FOSC/64
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29 | //0001= SPI Master mode, clock = FOSC/16
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30 | //0000= SPI Master mode, clock = FOSC/4
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31 | PIR1bits.SSPIF=0; //1= The transmission/reception is complete(must be cleared in software)
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32 | //0= wating to transmit/receive
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33 | TRISCbits.TRISC7=0; // Serial Data Out
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34 | TRISBbits.TRISB0=1; // Serial Data In
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35 | //CLK
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36 | TRISBbits.TRISB1=0;
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37 | //SS
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38 | TRISDbits.TRISD5=0;
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39 | }
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40 | int SPI_MASTER_WRITE(void)
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41 | {
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42 | INTCONbits.GIEH = 0;
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43 | TRISDbits.TRISD5=0;
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44 | SSPBUF = u08LSend_Data; // load the register SSPBUF
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45 | if ( SSPCON1bits.SSPOV) // test if write collision occurred
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46 | {
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47 | return ( -1 ); // if WCOL bit is set return negative #
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48 | }
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49 | else
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50 | {
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51 | while(!SSPSTATbits.BF) // control wenn the register is full
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52 |
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53 | TRISDbits.TRISD5=1; // CS
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54 | u08LSend_Data= SSPBUF;
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55 |
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56 | SSPSTATbits.BF=0; //
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57 | return SSPBUF;
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58 | }
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59 | INTCONbits.GIEH = 1;
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60 | }
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61 | /////Slave
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62 | #include "p18F4550.h"
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63 | #include <stdio.h>
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64 | #include <delays.h>
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65 | #include "Spi_Init.h"
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66 | #include "PortConfiguration.h"
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67 |
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68 | void SPI_INIT_SLAVE(void)
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69 | {
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70 | SSPSTATbits.SMP=0 ; // SPM must be cleared when SPI is used in Slave mode
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71 |
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72 | SSPSTATbits.CKE=0 ; //1= Transmit occurs on transition from active to Idle clock state
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73 | //0= transmit occurs on transition from Idle to active clock state
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74 | SSPCON1bits.WCOL=0 ; //1= The SSPBUF register is written while it is still transmitting the previous word (must be clear in Software)
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75 | //0= No collision
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76 | SSPCON1bits.SSPEN= 1; //1= Enables serial port and configures SCK, SDO, SDI and SS as serial port pins
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77 | //0= Disables serial port and configures these pins as I/O port pins
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78 | SSPCON1bits.CKP=1; //1= Idle state for clock is a high level
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79 | //0= Idle state for clock is a low level
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80 | //SSPM3:SSPM0: Master sychronous Serial Port Mode Select bits
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81 | SSPCON1bits.SSPM3= 0; //0101= SPI Slave mode, clock =SCK pin, SS pin control disabled, ss can be used as I/O pin
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82 | SSPCON1bits.SSPM2= 1; //0100= SPI slave mode, clock =SCK pin, SS pin control enabled
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83 | SSPCON1bits.SSPM1= 0; //0011= SPI Master mode, clock = TMR2 output/2
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84 | SSPCON1bits.SSPM0= 1; //0010= SPI Master mode, clock = FOSC/64
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85 | //0001= SPI Master mode, clock = FOSC/16
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86 | //0000= SPI Master mode, clock = FOSC/4
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87 | PIR1bits.SSPIF=0; //1= The transmission/reception is complete(must be cleared in software)
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88 | //0= wating to transmit/receive
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89 | TRISCbits.RC7=1; // Serial Data Out
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90 | TRISBbits.RB0=0; // Serial Data In
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91 | //CLK
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92 | TRISBbits.TRISB1=1;
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93 | //SS
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94 | TRISDbits.TRISD5=1;
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95 | }
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96 |
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97 | int SPI_SLAVE_READ( void )
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98 | {
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99 | SSP1BUF = 0x00; // initiate bus cycle
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100 | while ( !SSP1STATbits.BF ); // wait until cycle complete
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101 | return ( SSP1BUF ); // return with byte read
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102 | }
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