Hallo, habe versucht die Global Clock einzubinden klappt aber nicht:
1 | entity MAIN_STRUKTUR is
|
2 |
|
3 | Port ( MASTER_CLK : in std_logic; -- 27 MHZ EINGANG
|
4 | MASTER_EINGANG : in STD_LOGIC_VECTOR (11 downto 0);
|
5 | MASTER_RESET : in STD_LOGIC;
|
6 | SYSTEM_CLK_200MHZ_P : in std_logic;
|
7 | SYSTEM_CLK_200MHZ_N : in std_logic;
|
8 | CLK_200MHZ : out std_logic;
|
9 | end MAIN_STRUKTUR;
|
10 |
|
11 | architecture Behavioral of MAIN_STRUKTUR is
|
12 |
|
13 | begin
|
14 | -- IBUFGDS: Differential Global Clock Input Buffer
|
15 | -- Spartan-6
|
16 | -- Xilinx HDL Language Template, version 11.3
|
17 |
|
18 | IBUFGDS_inst : IBUFGDS
|
19 | generic map (
|
20 | DIFF_TERM => FALSE, -- Differential Termination
|
21 | IOSTANDARD => "DEFAULT")
|
22 | port map (
|
23 | O => CLK_200MHZ, -- Clock buffer output
|
24 | I => SYSTEM_CLK_200MHZ_P, -- Diff_p clock buffer input (connect directly to top-level port)
|
25 | IB => SYSTEM_CLK_200MHZ_N -- Diff_n clock buffer input (connect directly to top-level port)
|
26 | );
|
27 |
|
28 | -- End of IBUFGDS_inst instantiation
|
29 |
|
30 | END Behavioral;
|
Hier bekomme ich folenden Fehler:
1 | ERROR:HDLCompiler:69 - "D:\VHDL TUTORIAL\SIMULATOR_PULS\MAIN_STRUKTUR.vhd" Line 136: <ibufgds> is not declared.
|
Wenn ich es über
1 | Begin [/Begin] mache kommt ein Syntax Fehler:
|
2 | [vhdl]
|
3 | ERROR:HDLCompiler:806 - "D:\VHDL TUTORIAL\SIMULATOR_PULS\MAIN_STRUKTUR.vhd" Line 60: Syntax error near "IBUFGDS_inst".
|
Was mache ich den Falsch?
Gruß
Igor