1 | void write_data_wiznet(int registers, unsigned int data) {
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2 | unsigned int address_l = 0;
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3 | unsigned int address_h = 0;
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4 |
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5 | address_l = get_AddressL(registers);
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6 | address_h = get_AddressH(registers);
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7 |
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8 | SPI &= ~SCS; // SCS low setzen -> Wiznet enabled
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9 | //WIZNET &= ~CS; // CS low setzen -> Wiznet enabled
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10 | //_delay_us(5);
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11 | write_spi(WIZNET_WRITE);
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12 | write_spi(address_h);
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13 | write_spi(address_l);
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14 | write_spi(data);
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15 | //WIZNET |= CS; // CS high setzen -> Wiznet disabled
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16 | SPI |= SCS; // SCS high setzen -> Wiznet disabled
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17 | //_delay_us(5);
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18 | }
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19 |
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20 | void init_spi() {
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21 | // MISO -> input; MOSI -> output; SCK -> output; SS -> output
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22 | SPI_DDR = 0xB0;
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23 |
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24 | SPI |= SCS; //set
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25 |
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26 | //SPI control register
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27 | SPCR = 0x50;
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28 | //SPI status register
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29 | SPSR = 0x00;
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30 |
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31 | //SPI data register
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32 | SPDR = 0x00;
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33 | }
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34 |
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35 | void init_wiznet() {
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36 | // hardware reset
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37 | WIZNET |= RESET; //set
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38 | _delay_ms(10);
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39 | WIZNET &= ~RESET; //reset
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40 | _delay_ms(30);
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41 | WIZNET |= RESET; //set
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42 |
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43 | // register reset
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44 | write_data_wiznet(MR, 0x80);
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45 |
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46 | // set gateway ip address
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47 | write_data_wiznet(GAR0, 192);
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48 | write_data_wiznet(GAR1, 168);
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49 | write_data_wiznet(GAR2, 0);
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50 | write_data_wiznet(GAR3, 1);
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51 |
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52 | // set subnet mask
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53 | write_data_wiznet(SUBR0, 255);
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54 | write_data_wiznet(SUBR1, 255);
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55 | write_data_wiznet(SUBR2, 255);
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56 | write_data_wiznet(SUBR3, 0);
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57 |
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58 | // set mac address
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59 | write_data_wiznet(SHAR0, 0x00);
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60 | write_data_wiznet(SHAR1, 0x08);
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61 | write_data_wiznet(SHAR2, 0xDC);
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62 | write_data_wiznet(SHAR3, 0x01);
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63 | write_data_wiznet(SHAR4, 0x02);
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64 | write_data_wiznet(SHAR5, 0x03);
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65 |
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66 | // set own ip address
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67 | write_data_wiznet(SIPR0, 192);
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68 | write_data_wiznet(SIPR1, 168);
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69 | write_data_wiznet(SIPR2, 0);
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70 | write_data_wiznet(SIPR3, 10);
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71 | }
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