1 | /************************************************************
|
2 | * RFM12B - Receiver *
|
3 | * Controller: AT90PWM316, 1MHz *
|
4 | ************************************************************/
|
5 |
|
6 | #include <avr/io.h>
|
7 | #include <stdlib.h>
|
8 | #include <util/delay.h>
|
9 | #include "SPI.h"
|
10 |
|
11 | #define write 0xB8
|
12 | #define read 0xB0
|
13 |
|
14 |
|
15 | void SPI_Master_Init(void) // SPI Initialisierung
|
16 | {
|
17 | DDRB |= (1<<PB1); // Set MOSI output
|
18 | DDRB &= ~(1<<PB0); // Set MISO input
|
19 | DDRB |= (1<<PB7); // Set SCK output
|
20 |
|
21 | DDRD |= (1<<PD3); // Set CS output
|
22 | PORTD |= (1<<PD3); // Set CS = high
|
23 |
|
24 | DDRC |= 0xFF; // PORTC = output
|
25 |
|
26 | SPCR &= ~(1<<DORD); // Send MSB first
|
27 | SPCR |= (1<<MSTR); // Controller = Master
|
28 | SPCR &= ~(1<<CPOL); // CLK positiv phase
|
29 | SPCR &= ~(1<<CPHA); // Sampling data @ rising edge
|
30 | SPCR |= (1<<SPR1); // CLK / 64 = 125kHz
|
31 |
|
32 | SPCR |= (1<<SPE); // SPI enable
|
33 |
|
34 | _delay_ms(500); // Power-on-delay 500ms
|
35 | }
|
36 |
|
37 |
|
38 | void SPI_transfer(char data)
|
39 | {
|
40 | SPDR = data; // write to FIFO
|
41 | while (!(SPSR & (1<<SPIF)));
|
42 | }
|
43 |
|
44 |
|
45 | void Receive (char command, char data)
|
46 | {
|
47 | PORTD &= ~(1<<PD3); // CS = Low
|
48 |
|
49 | SPDR = command; // Command read FIFO
|
50 | while (!(SPSR & (1<<SPIF)));
|
51 |
|
52 | SPDR = data; // Write dummybyte
|
53 | while (!(SPSR & (1<<SPIF)));
|
54 |
|
55 | PORTC = SPDR; // Ausgabe 8 LEDs am PORTC
|
56 |
|
57 | PORTD |= (1<<PD3); // CS = High
|
58 | }
|
59 |
|
60 | void rfm12_init(void)
|
61 | {
|
62 | _delay_ms(100); // wait until Power On Reset (POR) done
|
63 | PORTD &= ~(1<<PD3); // CS = Low
|
64 |
|
65 | SPI_transfer(0x80); // Configuration Setting Command
|
66 | SPI_transfer(0xE7); // 868 MHz, 12pF, enable Tx + Rx
|
67 |
|
68 | SPI_transfer(0x82); // Power Management Command
|
69 | SPI_transfer(0xD9); // Enable: receiver, base band block, synthesizer, crystall oszillator. Disable: clock output of CLK pin
|
70 |
|
71 | SPI_transfer(0xA6); // Frequency Setting Command
|
72 | SPI_transfer(0x7C); // Set Frequency to 868,3 MHz
|
73 |
|
74 | SPI_transfer(0xC6); // Data Rate Command
|
75 | SPI_transfer(0x47); // 2400 kBaud
|
76 |
|
77 | SPI_transfer(0x94); // Receiver Control Commmand
|
78 | SPI_transfer(0xA4);
|
79 |
|
80 | SPI_transfer(0xC2); // Data Filter Command
|
81 | SPI_transfer(0xAC);
|
82 |
|
83 | SPI_transfer(0xCA); // FIFO & Reset Mode Command
|
84 | SPI_transfer(0x81);
|
85 |
|
86 | SPI_transfer(0xC4); // AFC Command
|
87 | SPI_transfer(0x83);
|
88 |
|
89 | SPI_transfer(0x98); // Tx Configuration Control Command
|
90 | SPI_transfer(0x50);
|
91 |
|
92 | SPI_transfer(0xE0); // Wake-up timer Command
|
93 | SPI_transfer(0x00);
|
94 |
|
95 | SPI_transfer(0xC8); // Low Duty-Cycle Command
|
96 | SPI_transfer(0x00);
|
97 |
|
98 | SPI_transfer(0xC0); // Low Battery Detector & Microcontroller Clock Divider Command
|
99 | SPI_transfer(0x00);
|
100 |
|
101 | PORTD |= (1<<PD3); // CS = High
|
102 | }
|
103 |
|
104 | void receiver_init(void)
|
105 | {
|
106 | PORTD &= ~(1<<PD3); // CS = Low
|
107 |
|
108 | SPI_transfer(0x82);
|
109 | SPI_transfer(0xC8); // Rx ON
|
110 |
|
111 | SPI_transfer(0xCA);
|
112 | SPI_transfer(0x83); // enable FIFO
|
113 |
|
114 | PORTD |= (1<<PD3); // CS = High
|
115 | }
|
116 |
|
117 | int main (void)
|
118 | {
|
119 | SPI_Master_Init();
|
120 | rfm12_init();
|
121 | receiver_init();
|
122 |
|
123 | while(1)
|
124 | {
|
125 | Receive (read, 0x00); // 0xB000
|
126 | }
|
127 | }
|