1 | #include <stdio.h>
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2 |
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3 | #define PMC_PCER 0xFFFFFC10 // Power Management Controller: Peripheral Clock Enable Register
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4 | #define TC_CMR0 0xFFFDC004 // Channel mode Register as seen in the datasheet for channel 0
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5 | #define TC_CMR1 0xFFFDC044 // Channel mode Register as seen in the datasheet for channel 1
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6 | #define TC_CMR2 0xFFFDC084 // Channel mode Register as seen in the datasheet for channel 2
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7 | #define TC_RC0 0xFFFDC01C // Register C as seen in the datasheet for channel 0
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8 | #define TC_RC1 0xFFFDC05C // Register C as seen in the datasheet for channel 1
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9 | #define TC_RC2 0xFFFDC09C // Register C as seen in the datasheet for channel 2
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10 | #define TC_RB0 0xFFFDC018 // Register B as seen in the datasheet for channel 0
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11 | #define TC_RB1 0xFFFDC058 // Register B as seen in the datasheet for channel 1
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12 | #define TC_RB2 0xFFFDC098 // Register B as seen in the datasheet for channel 2
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13 | #define TC_RA0 0xFFFDC014 // Register A as seen in the datasheet for channel 0
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14 | #define TC_RA1 0xFFFDC054 // Register A as seen in the datasheet for channel 1
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15 | #define TC_RA2 0xFFFDC094 // Register A as seen in the datasheet for channel 2
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16 | #define TC_CCR0 0xFFFDC000 // Channel Control Register as seen in the datasheet for channel 0
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17 | #define TC_CCR1 0xFFFDC040 // Channel Control Register as seen in the datasheet for channel 1
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18 | #define TC_CCR2 0xFFFDC080 // Channel Control Register as seen in the datasheet for channel 2
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19 | #define PIO_PDR 0xFFFFF404 // PIO Controller PIO Enable Register for Port PIOA
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20 | #define PIO_ASR 0xFFFFF470 // PIO Peripheral A Select Register for Port PIOA
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21 | #define TC_IER0 0xFFFDC024 // Interrupt Enable Register for Channel 0
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22 |
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23 | #define IO_WR32(adress, value) (*((volatile unsigned long *) (adress)) = (value))
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24 | #define IO_RD32(adress) (*((volatile unsigned long *) adress))
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25 | #define IO_SET_MASK32(adress, mask) IO_WR32((adress), IO_RD32((adress)) | (mask))
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26 |
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27 | void pal_pwm_start(){
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28 |
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29 | // Channel-Pin-Matching:
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30 | // PA26: Peripheral A: TIOA0, Peripheral B: ERX3
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31 | // Timer/Counter Channel 0: Output: TIOA0, TIOB0
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32 | // Timer1: TC0, TC1, TC2: TCLK0-TCLK2, TIOA0-TIOA2, TIOB0-TIOB2
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33 | // PA0 - PA31: Parallel I/O Controller A (PIOA)
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34 |
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35 | // Power Management Controller (PMC): Peripherial Clock Enable Register
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36 | // - activate the clock signal for T/C 0 (bit 17 to value 1b)
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37 | IO_WR32(PMC_PCER, (1<<17)); // Peripheral ID (PID) 17 belongs to Timer/Counter 0 and to Signal TIOA0
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38 | IO_WR32(PMC_PCER, (1<<2)); // Parallel I/O Controller A (PIOA)
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39 |
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40 | // T/C Channel Control Register for Channel 0:
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41 | // - disable the clock signal: CLKDIS-Bit (bit 1 to value 1)
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42 | IO_WR32(TC_CCR0, (1<<1));
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43 |
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44 | // PIO Disable Register for I/O-Port PIOA
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45 | // - disable GPIO-functionality for Pins PA26 and PA27 and enable their Peripheral function: Set Bit 26 to value 1
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46 | IO_WR32(PIO_PDR, (1<<26));
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47 |
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48 | // Peripheral A Select Register
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49 | // - enable Peripheral A instead of Peripheral B for Pins PA26: Set Bit 26 to value 1
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50 | IO_WR32(PIO_ASR, (1<<26));
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51 |
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52 | // T/C Channel Mode Register for Channel 0:
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53 | // - set the Operating Mode to WAVEFORM: WAVE-Bit (bit 15 to value 1b)
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54 | // - set the waveform to "up-mode with automatic trigger on RC compare": WAVSEL-Bits (bits 13-14 to value 10b = 2d)
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55 | // - set the Clock Signal to MCKL / 2 (TIMER_CLOCK1): TCCLKS-Bits (bits 0-2 to value 000b = 0d)
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56 | // - set the RA Compare Effect on TIOA output level to toogle: ACPA-bits (bit 16, 17 to value 11b = 3d)
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57 | // - set the RC Compare Effect on TIOA counter to clear: ACPC-Bits (bit 18, 19 to value 10b = 2d)
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58 | IO_WR32(TC_CMR0, (1<<15));
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59 | IO_WR32(TC_CMR0, (0<<14) | (1<<13));
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60 | IO_WR32(TC_CMR0, (0<<2) | (0<<1) | (0<<0));
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61 | IO_WR32(TC_CMR0, (1<<17) | (1<<16));
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62 | IO_WR32(TC_CMR0, (0<<19) | (1<<18));
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63 |
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64 | // T/C Interrupt Enable Register for Channel 0:
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65 | // - set the RC Compare interrupt (CPCS)
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66 | // - set the RA Compare interrupt (CPAS)
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67 | //IO_WR32(TC_IER0, (1<<4));
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68 | //IO_WR32(TC_IER0, (1<<2));
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69 |
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70 | // T/C Register C for Channel 0:
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71 | // - set the "reset value register" to 2^11: Register C to value 2^11d = 2048d (cuts down the 16-bit-resolution to 11-bit)
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72 | IO_WR32(TC_RC0, 2048);
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73 |
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74 | // T/C Register A for Channel 0:
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75 | // - set the LOW-to-HIGH threshold to 2^11 / 2 (50% duty cycle) --> value 1024d
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76 | IO_WR32(TC_RA0, 1024);
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77 |
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78 | // T/C Channel Control Register for Channel 0:
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79 | // - enable the clock signal: CLKEN-Bit, CLKDIS-Bit (bit 1 to value 0 and bit 0 to value 1)
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80 | IO_WR32(TC_CCR0, (0<<1)); // unset disable-bit
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81 | IO_WR32(TC_CCR0, (1<<0)); // set enable-bit
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82 | }
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