1 | #include <mega32.h>
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2 | #include <stdio.h>
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3 | #include <delay.h>
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4 |
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5 |
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6 | unsigned char zahl_0=0x3f;
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7 | unsigned char zahl_1=0x86;
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8 | unsigned char zahl_2=0x5b;
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9 | unsigned char zahl_3=0x4f;
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10 | unsigned char zahl_4=0x66;
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11 | unsigned char zahl_5=0x6d;
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12 | unsigned char zahl_6=0x7d;
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13 | unsigned char zahl_7=0x87;
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14 | unsigned char zahl_8=0x00;
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15 | unsigned char zahl_9=0x6f;
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16 |
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17 | interrupt [EXT_INT0] void ext_int0_isr(void) //Externer Interrupt (Tasten einlesen)
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18 | {
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19 |
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20 |
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21 | }
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22 |
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23 | void main(void)
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24 | {
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25 | // Declare your local variables here
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26 |
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27 | // Input/Output Ports initialization
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28 | // Port A initialization
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29 |
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30 | DDRA=(1<<DDA7) | (1<<DDA6) | (1<<DDA5) | (1<<DDA4) | (1<<DDA3) | (1<<DDA2) | (1<<DDA1) | (1<<DDA0);
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31 | PORTA=(1<<PORTA7) | (1<<PORTA6) | (1<<PORTA5) | (1<<PORTA4) | (1<<PORTA3) | (1<<PORTA2) | (1<<PORTA1) | (1<<PORTA0);
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32 |
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33 | // Port B initialization
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34 |
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35 | DDRB=(0<<DDB7) | (0<<DDB6) | (0<<DDB5) | (0<<DDB4) | (0<<DDB3) | (0<<DDB2) | (0<<DDB1) | (0<<DDB0);
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36 | PORTB=(0<<PORTB7) | (0<<PORTB6) | (0<<PORTB5) | (0<<PORTB4) | (0<<PORTB3) | (0<<PORTB2) | (0<<PORTB1) | (0<<PORTB0);
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37 |
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38 | // Port C initialization
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39 | DDRC=(0<<DDC7) | (0<<DDC6) | (0<<DDC5) | (0<<DDC4) | (0<<DDC3) | (0<<DDC2) | (0<<DDC1) | (0<<DDC0);
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40 | PORTC=(0<<PORTC7) | (0<<PORTC6) | (0<<PORTC5) | (0<<PORTC4) | (0<<PORTC3) | (0<<PORTC2) | (0<<PORTC1) | (0<<PORTC0);
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41 |
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42 | // Port D initialization
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43 | DDRD=(0<<DDD7) | (0<<DDD6) | (0<<DDD5) | (0<<DDD4) | (0<<DDD3) | (0<<DDD2) | (0<<DDD1) | (0<<DDD0);
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44 | PORTD=(0<<PORTD7) | (0<<PORTD6) | (0<<PORTD5) | (0<<PORTD4) | (0<<PORTD3) | (0<<PORTD2) | (0<<PORTD1) | (0<<PORTD0);
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45 |
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46 | // Timer/Counter 0 initialization
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47 | // Clock source: System Clock
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48 | // Clock value: Timer 0 Stopped
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49 | // Mode: Normal top=0xFF
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50 | // OC0 output: Disconnected
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51 | TCCR0=(0<<WGM00) | (0<<COM01) | (0<<COM00) | (0<<WGM01) | (0<<CS02) | (0<<CS01) | (0<<CS00);
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52 | TCNT0=0x00;
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53 | OCR0=0x00;
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54 |
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55 | // Timer/Counter 1 initialization
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56 | // Clock source: System Clock
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57 | // Clock value: Timer1 Stopped
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58 | // Mode: Normal top=0xFFFF
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59 | // OC1A output: Discon.
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60 | // OC1B output: Discon.
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61 | // Noise Canceler: Off
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62 | // Input Capture on Falling Edge
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63 | // Timer1 Overflow Interrupt: Off
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64 | // Input Capture Interrupt: Off
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65 | // Compare A Match Interrupt: Off
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66 | // Compare B Match Interrupt: Off
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67 | TCCR1A=(0<<COM1A1) | (0<<COM1A0) | (0<<COM1B1) | (0<<COM1B0) | (0<<WGM11) | (0<<WGM10);
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68 | TCCR1B=(0<<ICNC1) | (0<<ICES1) | (0<<WGM13) | (0<<WGM12) | (0<<CS12) | (0<<CS11) | (0<<CS10);
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69 | TCNT1H=0x00;
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70 | TCNT1L=0x00;
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71 | ICR1H=0x00;
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72 | ICR1L=0x00;
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73 | OCR1AH=0x00;
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74 | OCR1AL=0x00;
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75 | OCR1BH=0x00;
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76 | OCR1BL=0x00;
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77 |
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78 | // Timer/Counter 2 initialization
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79 | // Clock source: System Clock
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80 | // Clock value: Timer2 Stopped
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81 | // Mode: Normal top=0xFF
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82 | // OC2 output: Disconnected
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83 | ASSR=0<<AS2;
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84 | TCCR2=(0<<PWM2) | (0<<COM21) | (0<<COM20) | (0<<CTC2) | (0<<CS22) | (0<<CS21) | (0<<CS20);
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85 | TCNT2=0x00;
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86 | OCR2=0x00;
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87 |
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88 | // Timer(s)/Counter(s) Interrupt(s) initialization
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89 | TIMSK=(0<<OCIE2) | (0<<TOIE2) | (0<<TICIE1) | (0<<OCIE1A) | (0<<OCIE1B) | (0<<TOIE1) | (0<<OCIE0) | (0<<TOIE0);
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90 |
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91 | // External Interrupt(s) initialization
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92 | // INT0: On
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93 | // INT0 Mode: Falling Edge
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94 | // INT1: Off
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95 | // INT2: Off
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96 | GICR|=(0<<INT1) | (1<<INT0) | (0<<INT2);
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97 | MCUCR=(0<<ISC11) | (0<<ISC10) | (1<<ISC01) | (0<<ISC00);
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98 | MCUCSR=(0<<ISC2);
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99 | GIFR=(0<<INTF1) | (1<<INTF0) | (0<<INTF2);
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100 |
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101 | // USART initialization
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102 | // USART disabled
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103 | UCSRB=(0<<RXCIE) | (0<<TXCIE) | (0<<UDRIE) | (0<<RXEN) | (0<<TXEN) | (0<<UCSZ2) | (0<<RXB8) | (0<<TXB8);
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104 |
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105 | // Analog Comparator initialization
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106 | // Analog Comparator: Off
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107 | ACSR=(1<<ACD) | (0<<ACBG) | (0<<ACO) | (0<<ACI) | (0<<ACIE) | (0<<ACIC) | (0<<ACIS1) | (0<<ACIS0);
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108 | SFIOR=(0<<ACME);
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109 |
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110 | // ADC initialization
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111 | // ADC disabled
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112 | ADCSRA=(0<<ADEN) | (0<<ADSC) | (0<<ADATE) | (0<<ADIF) | (0<<ADIE) | (0<<ADPS2) | (0<<ADPS1) | (0<<ADPS0);
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113 |
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114 | // SPI initialization
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115 | // SPI disabled
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116 | SPCR=(0<<SPIE) | (0<<SPE) | (0<<DORD) | (0<<MSTR) | (0<<CPOL) | (0<<CPHA) | (0<<SPR1) | (0<<SPR0);
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117 |
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118 | // TWI initialization
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119 | // TWI disabled
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120 | TWCR=(0<<TWEA) | (0<<TWSTA) | (0<<TWSTO) | (0<<TWEN) | (0<<TWIE);
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121 |
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122 | // Global enable interrupts
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123 | #asm("sei")
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124 |
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125 | while (1)
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126 | {
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127 | PORTA = zahl_0; // 0
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128 | delay_ms(2000); // Wait for 1s
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129 | PORTA = zahl_1; // 1
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130 | delay_ms(2000); // Wait for 1s
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131 | PORTA = zahl_2; // 2
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132 | delay_ms(2000); // Wait for 1s
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133 | PORTA = zahl_3; // 3
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134 | delay_ms(2000); // Wait for 1s
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135 | PORTA = zahl_4; // 4
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136 | delay_ms(2000); // Wait for 1s
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137 | PORTA = zahl_5; // 5
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138 | delay_ms(2000); // Wait for 1s
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139 | PORTA = zahl_6; // 6
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140 | delay_ms(2000); // Wait for 1s
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141 | PORTA = zahl_7; // 7
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142 | delay_ms(2000); // Wait for 1s
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143 | PORTA = zahl_8; // 8
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144 | delay_ms(2000); // Wait for 1s
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145 | PORTA = zahl_9; // 9
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146 | delay_ms(2000); // Wait for 1s
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147 | }
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148 | }
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