1 | #define DMA_SPI2_RX_STREAM DMA1_Stream3
|
2 | #define DMA_SPI2_TX_STREAM DMA1_Stream4
|
3 |
|
4 | void stm32_dma_transfer(
|
5 | UINT receive, /* FALSE for buff->SPI, TRUE for SPI->buff */
|
6 | const BYTE *buff, /* receive TRUE : 512 byte data block to be transmitted
|
7 | receive FALSE : Data buffer to store received data */
|
8 | UINT btr /* receive TRUE : Byte count (must be multiple of 2)
|
9 | receive FALSE : Byte count (must be 512) */
|
10 | )
|
11 | {
|
12 | DMA_InitTypeDef DMA_InitStructure;
|
13 | WORD rw_workbyte[] = { 0xffff };
|
14 |
|
15 | //enable clock
|
16 | RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_DMA1, ENABLE);
|
17 |
|
18 | //start with a blank DMA configuration
|
19 | DMA_DeInit(DMA_SPI2_RX_STREAM); //SPI-RX
|
20 | DMA_DeInit(DMA_SPI2_TX_STREAM); //SPI-TX
|
21 |
|
22 | //only these parameters differ from default values
|
23 | DMA_InitStructure.DMA_Channel = DMA_Channel_0;
|
24 | DMA_InitStructure.DMA_PeripheralBaseAddr = (DWORD) & (SPI2->DR);
|
25 | DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
26 | DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
27 | DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
28 | DMA_InitStructure.DMA_BufferSize = btr;
|
29 | DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
|
30 | DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
|
31 |
|
32 | if (receive){
|
33 | // DMA1-Channel0-Stream3 configured as SPI2-RX
|
34 | DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff;
|
35 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
36 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
37 | DMA_Init(DMA_SPI2_RX_STREAM, &DMA_InitStructure);
|
38 |
|
39 | // DMA1-Channel0-Stream4 configured as SPI2-TX
|
40 | DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte;
|
41 | DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
|
42 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
43 | DMA_Init(DMA_SPI2_TX_STREAM, &DMA_InitStructure);
|
44 | }
|
45 | else {
|
46 | // DMA1-Channel0-Stream3 configured as SPI2-RX
|
47 | DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)rw_workbyte;
|
48 | DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
|
49 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
|
50 | DMA_Init(DMA_SPI2_RX_STREAM, &DMA_InitStructure);
|
51 |
|
52 | // DMA1-Channel0-Stream4 configured as SPI2-TX
|
53 | DMA_InitStructure.DMA_Memory0BaseAddr = (DWORD)buff;
|
54 | DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
|
55 | DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
|
56 | DMA_Init(DMA_SPI2_TX_STREAM, &DMA_InitStructure);
|
57 | }
|
58 |
|
59 | //Enable DMA RX/TX
|
60 | DMA_Cmd(DMA_SPI2_RX_STREAM, ENABLE); //SPI-RX
|
61 | DMA_Cmd(DMA_SPI2_TX_STREAM, ENABLE); //SPI-TX
|
62 |
|
63 | /* Enable SPI TX/RX request */
|
64 | SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
|
65 |
|
66 | /* Wait until DMA1_Channel 2 Receive Complete */
|
67 | //while (DMA_GetFlagStatus(DMA_SPI2_RX_STREAM, DMA_FLAG_TCIF4) == RESET) { ; }
|
68 |
|
69 | //Disable DMA RX/TX
|
70 | DMA_Cmd(DMA_SPI2_RX_STREAM, DISABLE); //SPI-RX
|
71 | DMA_Cmd(DMA_SPI2_TX_STREAM, DISABLE); //SPI-TX
|
72 |
|
73 | /* Disable SPI RX/TX request */
|
74 | SPI_I2S_DMACmd(SPI2, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);
|
75 | }
|