Problem mit Timing Constraint bei Xilinx

[Ralf (Gast)]

Das DCM constraint wird nicht angenommen, weil die Referenz auf die 
Clock nicht alleinig steht, sondern es noch ein timing ignore zu anderen 
Takten gibt. So lese ich das jedenfalls.

Frage: Wie behebe ich es?  Muss ich die CLK nochmal irgendwie einpacken, 
um das TIG zusetzen?

Es gibt insgesamt 4 Takte im Design und ich habe von jedem zu jedem ein 
TIG gesetzt.

<code>

WARNING:ConstraintSystem - TNM : CLK_PLL was distributed to a DCM but 
new TNM
   constraints were not derived. The requirement for derived TNM 
constraints is
   that the distributed TNM is referenced by no more than a single 
PERIOD
   constraint. Non-PERIOD referencers are also not allowed. This TNM is 
used in
   the following user groups or specifications:

   <TIMESPEC TS_CLK_PLL = PERIOD "CLK_PLL" 5.0 ns HIGH 50%;>
   [PDM_MOD.ucf(462)]
   <TIMESPEC TS_IGNORE = FROM DATA_IN_CLK TO CLK_PLL TIG;>
   [PDM_MOD.ucf(471)]
   <TIMESPEC TS_IGNORE = FROM VPIF_CLKO2_FROM_DAVINCI TO CLK_PLL TIG;>
   [PDM_MOD.ucf(475)]
   <TIMESPEC TS_IGNORE = FROM CLK_PLL TO VPIF_CLKO2_FROM_DAVINCI TIG;>
   [PDM_MOD.ucf(478)]
   <TIMESPEC TS_IGNORE = FROM CLK_PLL TO DATA_IN_CLK TIG;>
   [PDM_MOD.ucf(479)]
   <TIMESPEC TS_IGNORE = FROM CLK_PLL TO EXT_PLL TIG;> 
[PDM_MOD.ucf(480)]
   <TIMESPEC TS_IGNORE = FROM EXT_PLL TO CLK_PLL TIG;> 
[PDM_MOD.ucf(484)]
WARNING:ConstraintSystem:190 - The TNM 'CLK_PLL', does not directly or
   indirectly drive any flip-flops, latches and/or RAMS and cannot be 
actively
   used by the referencing Period constraint 'TS_CLK_PLL'. If clock 
manager
   blocks are directly or indirectly driven, a new TNM and PERIOD are 
derived
   only if the PERIOD constraint is the only referencing constraint and 
if an
   output of the clock manager block drives flip-flops, latches or RAMs.
   This TNM is used in the following user groups and/or specifications:
   <TIMESPEC TS_CLK_PLL = PERIOD "CLK_PLL" 5.0 ns HIGH 50%;>
   [PDM_MOD.ucf(462)]
   <TIMESPEC TS_IGNORE = FROM DATA_IN_CLK TO CLK_PLL TIG;>
   [PDM_MOD.ucf(471)]

</code>

Idee?

[FPGA-Progger (Gast)]

Der Xilinx - Constraints Guide beschreibt das eigentlich sehr genau