1 | uint32_t HDP = 479;
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2 | uint32_t HT = 531; //horiz. total period (display + non-display) in pixel clocks
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3 | uint32_t HPS = 43; //byte of the non-display period between the start of the horiz. sync (LLINE) signal and first
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4 | //display data = "hor. back porch + hor. pulse width?"
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5 | uint32_t LPS = 8; //horizontal sync pulse (LLINE) start location in pixel clocks = "front porch?"
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6 | uint32_t HPW = 10; //horizontal sync pulse width (= (HPW + 1) pixels )
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7 | uint32_t VDP = 271;
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8 | uint32_t VT = 288;
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9 | uint32_t VPS = 12; //Vertical Sync Pulse Width = (VPW + 1) lines
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10 | uint32_t FPS = 4; //vertical sync pulse (LFRAME) start location in lines.
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11 | uint32_t VPW = 10;
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12 |
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13 |
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14 | void Lcd_Init(void)
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15 | {
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16 | gpio_set_pin_high(LCD_CS); // LCD_CS = 1;
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17 | gpio_set_pin_high(LCD_RD);
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18 | gpio_set_pin_high(LCD_WR);
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19 |
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20 | gpio_set_pin_high(LCD_RES);
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21 | mdelay(100);
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22 | gpio_set_pin_low(LCD_RES);
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23 | mdelay(5);
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24 | gpio_set_pin_high(LCD_RES);
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25 | mdelay(5);
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26 | gpio_set_pin_high(LCD_CS);
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27 | //gpio_set_pin_high(LCD_RD);
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28 | //gpio_set_pin_high(LCD_WR);
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29 | mdelay(5);
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30 |
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31 | gpio_set_pin_low(LCD_CS);
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32 |
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33 | LCD_WR_REG(0x00E2); //PLL multiplier, set PLL clock to 120M
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34 | // LCD_WR_DATA(0x002d); //N=0x36 for 6.5M, 0x23 for 10M crystal
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35 | LCD_WR_DATA(0x0023); //N=0x36 for 6.5M, 0x23 for 10M crystal
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36 | LCD_WR_DATA(0x0002);
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37 | LCD_WR_DATA(0x0004);
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38 | mdelay(1);
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39 |
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40 | LCD_WR_REG(0x00E0);
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41 | LCD_WR_DATA(0x0001); // 03
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42 | mdelay(10);
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43 |
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44 |
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45 | LCD_WR_REG(0x00E0);
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46 | LCD_WR_DATA(0x0003); // 03
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47 | mdelay(10);
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48 |
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49 | LCD_WR_REG(0x0001); // software reset
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50 | mdelay(100);
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51 |
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52 | LCD_WR_REG(0x00E6); //PLL setting for PCLK, depends on resolution
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53 | LCD_WR_DATA(0x0000);
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54 | LCD_WR_DATA(0x00ff);
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55 | LCD_WR_DATA(0x00be);
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56 |
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57 | LCD_WR_REG(0x00B0); //LCD SPECIFICATION
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58 | LCD_WR_DATA(0x0020); //24bit to panel
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59 | LCD_WR_DATA(0x0000);
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60 | LCD_WR_DATA((HDP>>8)&0X00FF); //Set HDP
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61 | LCD_WR_DATA(HDP&0X00FF);
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62 | LCD_WR_DATA((VDP>>8)&0X00FF); //Set VDP
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63 | LCD_WR_DATA(VDP&0X00FF);
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64 | LCD_WR_DATA(0x0000);
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65 | mdelay(5);
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66 |
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67 | LCD_WR_REG(0x00B4); //HSYNC ///531[d] = 213[h]
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68 | LCD_WR_DATA((HT>>8) & 0x00FF); //Set HT 2
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69 | LCD_WR_DATA(HT & 0x00FF);
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70 | LCD_WR_DATA((HPS>>8) & 0x00FF); //Set HPS
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71 | LCD_WR_DATA(HPS&0X00FF);
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72 | LCD_WR_DATA(HPW); //Set HPW
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73 | LCD_WR_DATA((LPS>>8)&0X00FF); //SetLPS
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74 | LCD_WR_DATA(LPS&0X00FF);
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75 | LCD_WR_DATA(0x0000);
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76 |
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77 | LCD_WR_REG(0x00B6); //VSYNC
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78 | LCD_WR_DATA((VT>>8)&0X00FF); //Set VT
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79 | LCD_WR_DATA(VT&0X00FF);
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80 | LCD_WR_DATA((VPS>>8)&0X00FF); //Set VPS
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81 | LCD_WR_DATA(VPS&0X00FF);
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82 | LCD_WR_DATA(VPW); //Set VPW
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83 | LCD_WR_DATA((FPS>>8)&0X00FF); //Set FPS
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84 | LCD_WR_DATA(FPS&0X00FF);
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85 |
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86 |
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87 | LCD_WR_REG(0x0036); //rotation
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88 | LCD_WR_DATA(0x0000);
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89 |
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90 | LCD_WR_REG(0x3A); //Set Pixel Format
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91 | LCD_WR_DATA(0x50);
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92 |
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93 |
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94 | LCD_WR_REG(0x00F0); //pixel data interface
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95 | LCD_WR_DATA(0x0003); // width: 16-bit (565 format)
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96 |
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97 | mdelay(5);
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98 |
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99 | LCD_WR_REG(0x0029); //display on
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100 |
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101 | LCD_WR_REG(0x00BE); //set PWM for B/L
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102 | LCD_WR_DATA(0x0006);
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103 | LCD_WR_DATA(0x00f0);
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104 | LCD_WR_DATA(0x0001);
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105 | LCD_WR_DATA(0x00f0);
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106 | LCD_WR_DATA(0x0000);
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107 | LCD_WR_DATA(0x0000);
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108 |
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109 | LCD_WR_REG(0x00d0);
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110 | LCD_WR_DATA(0x000d);
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111 |
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112 | //----------LCD RESET---GPIO0-------------------//
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113 | LCD_WR_REG(0x00B8);
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114 | LCD_WR_DATA(0x0000); //GPIO3=input, GPIO[2:0]=output
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115 | LCD_WR_DATA(0x0001); //GPIO0 normal
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116 |
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117 | LCD_WR_REG(0x00BA);
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118 | LCD_WR_DATA(0x0000);
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119 | }
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