1 | uint8_t data[1] = { 0 };
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2 | twim_write (twim,data,0,chip_addr,0);
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3 | .
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4 | .
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5 | .
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6 |
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7 | status_code_t twim_write (volatile avr32_twim_t *twim, uint8_t const *buffer,
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8 | uint32_t nbytes, uint32_t saddr, bool tenbit)
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9 | {
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10 | // Reset the TWIM module to clear the THR register
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11 | twim->cr = AVR32_TWIM_CR_MEN_MASK;
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12 | twim->cr = AVR32_TWIM_CR_SWRST_MASK;
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13 | twim->cr = AVR32_TWIM_CR_MDIS_MASK;
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14 | // Set pointer to TWIM instance for IT
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15 | twim_inst = twim;
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16 | // Disable the TWIM interrupts
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17 | twim_disable_interrupt (twim_inst);
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18 | // get a pointer to applicative data
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19 | twim_tx_data = buffer;
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20 | // set the number of bytes to transmit
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21 | twim_tx_nb_bytes = nbytes;
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22 | // Set next transfer to false
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23 | twim_next = false;
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24 | // Initialize bus transfer status
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25 | transfer_status = TWI_SUCCESS;
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26 | // set the command to start the transfer
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27 | twim_inst->cmdr = (saddr << AVR32_TWIM_CMDR_SADR_OFFSET)
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28 | | (nbytes << AVR32_TWIM_CMDR_NBYTES_OFFSET)
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29 | | (AVR32_TWIM_CMDR_VALID_MASK)
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30 | | (AVR32_TWIM_CMDR_START_MASK)
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31 | | (AVR32_TWIM_CMDR_STOP_MASK)
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32 | | ((tenbit ? 1 : 0) << AVR32_TWIM_CMDR_TENBIT_OFFSET)
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33 | | (0 << AVR32_TWIM_CMDR_READ_OFFSET);
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34 | // mask NACK and TXRDY interrupts
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35 | twim_it_mask = AVR32_TWIM_IER_NAK_MASK | AVR32_TWIM_IER_TXRDY_MASK;
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36 | // update IMR through IER
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37 | twim_inst->ier = twim_it_mask;
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38 | // Enable master transfer
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39 | twim_inst->cr = AVR32_TWIM_CR_MEN_MASK;
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40 | // Enable all interrupts
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41 | cpu_irq_enable ();
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42 | // send data
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43 | while (!(transfer_status) && !(twim_status ())) {
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44 | cpu_relax();
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45 | }
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46 | #if AVR32_TWIM_H_VERSION > 101 // Removed in twim100 module due to IC bug
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47 | // Disable master transfer
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48 | twim->cr = AVR32_TWIM_CR_MDIS_MASK;
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49 | #endif
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50 | if (transfer_status == TWI_RECEIVE_NACK
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51 | || transfer_status == TWI_ARBITRATION_LOST) {
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52 | return ERR_IO_ERROR;
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53 | }
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54 | return STATUS_OK;
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55 | }
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