1 | Library IEEE;
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2 | use IEEE.std_logic_1164.all;
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3 | use IEEE.std_logic_arith.all;
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4 | entity Zbuscon is
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5 | Port (
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6 | CLK, IOR, IOW, RSTDRV, CSZ: in std_logic;
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7 | RD, WR, CNT, COUNT2, COUNT1, COUNT0: buffer std_logic
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8 | );
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9 | end Zbuscon;
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10 |
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11 |
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12 | architecture Zbuscon_behav of Zbuscon is
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13 | signal COUNT0_CLK_ctrl, COUNT0_ACLR_ctrl, RD_bar, WR_bar, CNT_D, CE_D,
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14 | CNTCLR_D, COUNT2_D, COUNT1_D, COUNT0_D, CNT_CLK, CNTCLR_ACLR,
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15 | CNTCLR_CLK, CE_ACLR, CE_CLK, CNTCLR, CE: std_logic;
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16 | signal CNT_FB, CE_FB, CNTCLR_FB, COUNT2_FB, COUNT1_FB, COUNT0_FB: std_logic
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17 | -- :='0'
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18 | ;
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19 |
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20 | Function to_std_logic(X: in Boolean) return Std_Logic is
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21 | variable ret : std_logic;
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22 | begin
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23 | if x then ret := '1'; else ret := '0'; end if;
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24 | return ret;
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25 | end to_std_logic;
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26 |
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27 | begin
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28 |
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29 | -- Register Section
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30 |
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31 | CNT <= CNT_FB;
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32 | process (CNT_CLK) begin
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33 | if CNT_CLK'event and CNT_CLK='1' then
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34 | CNT_FB <= CNT_D;
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35 | end if;
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36 | end process;
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37 |
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38 | CE <= CE_FB;
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39 | process (CE_CLK, CE_ACLR) begin
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40 | if CE_ACLR='1' then
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41 | CE_FB <= '0';
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42 | elsif CE_CLK'event and CE_CLK='1' then
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43 | CE_FB <= CE_D;
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44 | end if;
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45 | end process;
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46 |
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47 | CNTCLR <= CNTCLR_FB;
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48 | process (CNTCLR_CLK, CNTCLR_ACLR) begin
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49 | if CNTCLR_ACLR='1' then
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50 | CNTCLR_FB <= '0';
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51 | elsif CNTCLR_CLK'event and CNTCLR_CLK='1' then
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52 | CNTCLR_FB <= CNTCLR_D;
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53 | end if;
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54 | end process;
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55 |
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56 | (COUNT2, COUNT1, COUNT0) <= std_logic_vector'(COUNT2_FB & COUNT1_FB &
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57 | COUNT0_FB);
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58 | process (COUNT0_CLK_ctrl, COUNT0_ACLR_ctrl) begin
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59 | if COUNT0_ACLR_ctrl='1' then
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60 | (COUNT2_FB, COUNT1_FB, COUNT0_FB) <= std_logic_vector'("000");
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61 | elsif COUNT0_CLK_ctrl'event and COUNT0_CLK_ctrl='1' then
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62 | (COUNT2_FB, COUNT1_FB, COUNT0_FB) <= std_logic_vector'(COUNT2_D &
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63 | COUNT1_D & COUNT0_D);
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64 | end if;
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65 | end process;
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66 |
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67 | -- Start of original equations
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68 | COUNT0_CLK_ctrl <= CLK;
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69 | COUNT0_ACLR_ctrl <= RSTDRV;
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70 | CE_D <= CSZ;
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71 | CE_CLK <= (IOR) and (IOW);
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72 | CE_ACLR <= CNTCLR;
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73 | CNTCLR_D <= to_std_logic(std_logic_vector'(COUNT2 & COUNT1 & COUNT0) =
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74 | "111");
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75 | CNTCLR_CLK <= CLK;
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76 | CNTCLR_ACLR <= RSTDRV;
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77 |
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78 |
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79 | process (CE, COUNT0, COUNT1, COUNT2)
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80 | begin
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81 | (COUNT2_D, COUNT1_D, COUNT0_D) <= std_logic_vector'("000");
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82 | if (not CE)='1' then
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83 | (COUNT2_D, COUNT1_D, COUNT0_D) <= std_logic_vector'(COUNT2 & COUNT1 &
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84 | COUNT0);
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85 | else
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86 | (COUNT2_D, COUNT1_D, COUNT0_D) <=
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87 | std_logic_vector'(unsigned(std_logic_vector'(COUNT2 & COUNT1 &
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88 | COUNT0)) + unsigned'("001"));
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89 | end if;
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90 | end process;
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91 | RD_bar <= RSTDRV or (not IOR and CNT);
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92 | WR_bar <= RSTDRV or (not IOW and CNT);
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93 | CNT_D <= to_std_logic(std_logic_vector'(COUNT2 & COUNT1 & COUNT0) = "000" or
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94 | std_logic_vector'(COUNT2 & COUNT1 & COUNT0) = "111");
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95 | CNT_CLK <= CLK;
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96 |
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97 |
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98 | -- Assignments added to explicitly combine the effects of
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99 | -- multiple drivers and negative assignments in the source
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100 | WR <= not WR_bar;
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101 | RD <= not RD_bar;
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102 | end Zbuscon_behav;
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