1 | /*** Include and Header files ******************************************************************************/
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2 |
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3 | #include <xc.h> //by Microchip
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4 | #include <p18f87K22.h> //by Microchip
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5 |
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6 | /*** Configuration PIC *********************************************************************************/
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7 |
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8 | // PIC18F87K22 Configuration Bit Settings
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9 | // Use project enums instead of #define for ON and OFF.
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10 |
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11 |
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12 | // PIC18F87K22 Configuration Bit Settings
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13 |
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14 | // 'C' source line config statements
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15 |
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16 | // #pragma config statements should precede project file includes.
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17 | // Use project enums instead of #define for ON and OFF.
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18 |
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19 | // CONFIG1L
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20 | #pragma config RETEN = OFF // VREG Sleep Enable bit (Disabled - Controlled by SRETEN bit)
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21 | #pragma config INTOSCSEL = HIGH // LF-INTOSC Low-power Enable bit (LF-INTOSC in High-power mode during Sleep)
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22 | #pragma config SOSCSEL = HIGH // SOSC Power Selection and mode Configuration bits (High Power SOSC circuit selected)
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23 | #pragma config XINST = OFF // Extended Instruction Set (Disabled)
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24 |
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25 | // CONFIG1H
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26 | #pragma config FOSC = INTIO2 // Oscillator (Internal RC oscillator)
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27 | #pragma config PLLCFG = ON // PLL x4 Enable bit (Enabled)
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28 | #pragma config FCMEN = OFF // Fail-Safe Clock Monitor (Disabled)
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29 | #pragma config IESO = OFF // Internal External Oscillator Switch Over Mode (Disabled)
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30 |
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31 | // CONFIG2L
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32 | #pragma config PWRTEN = OFF // Power Up Timer (Disabled)
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33 | #pragma config BOREN = SBORDIS // Brown Out Detect (Enabled in hardware, SBOREN disabled)
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34 | #pragma config BORV = 3 // Brown-out Reset Voltage bits (1.8V)
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35 | #pragma config BORPWR = ZPBORMV // BORMV Power level (ZPBORMV instead of BORMV is selected)
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36 |
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37 | // CONFIG2H
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38 | #pragma config WDTEN = SWDTDIS // Watchdog Timer (WDT enabled in hardware; SWDTEN bit disabled)
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39 | #pragma config WDTPS = 1048576 // Watchdog Postscaler (1:1048576)
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40 |
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41 | // CONFIG3L
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42 | #pragma config RTCOSC = 0 // RTCC Clock Select (RTCC uses SOSC)
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43 | #pragma config EASHFT = ON // External Address Shift bit (Address Shifting enabled)
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44 | #pragma config ABW = MM // Address Bus Width Select bits (8-bit address bus)
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45 | #pragma config BW = 16 // Data Bus Width (16-bit external bus mode)
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46 | #pragma config WAIT = OFF // External Bus Wait (Disabled)
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47 |
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48 | // CONFIG3H
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49 | #pragma config CCP2MX = PORTC // CCP2 Mux (RC1)
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50 | #pragma config ECCPMX = PORTE // ECCP Mux (Enhanced CCP1/3 [P1B/P1C/P3B/P3C] muxed with RE6/RE5/RE4/RE3)
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51 | #pragma config MSSPMSK = MSK7 // MSSP address masking (7 Bit address masking mode)
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52 | #pragma config MCLRE = ON // Master Clear Enable (MCLR Enabled, RG5 Disabled)
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53 |
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54 | // CONFIG4L
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55 | #pragma config STVREN = ON // Stack Overflow Reset (Enabled)
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56 | #pragma config BBSIZ = BB2K // Boot Block Size (2K word Boot Block size)
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57 |
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58 | // CONFIG5L
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59 | #pragma config CP0 = OFF // Code Protect 00800-03FFF (Disabled)
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60 | #pragma config CP1 = OFF // Code Protect 04000-07FFF (Disabled)
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61 | #pragma config CP2 = OFF // Code Protect 08000-0BFFF (Disabled)
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62 | #pragma config CP3 = OFF // Code Protect 0C000-0FFFF (Disabled)
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63 | #pragma config CP4 = OFF // Code Protect 10000-13FFF (Disabled)
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64 | #pragma config CP5 = OFF // Code Protect 14000-17FFF (Disabled)
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65 | #pragma config CP6 = OFF // Code Protect 18000-1BFFF (Disabled)
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66 | #pragma config CP7 = OFF // Code Protect 1C000-1FFFF (Disabled)
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67 |
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68 | // CONFIG5H
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69 | #pragma config CPB = OFF // Code Protect Boot (Disabled)
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70 | #pragma config CPD = OFF // Data EE Read Protect (Disabled)
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71 |
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72 | // CONFIG6L
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73 | #pragma config WRT0 = OFF // Table Write Protect 00800-03FFF (Disabled)
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74 | #pragma config WRT1 = OFF // Table Write Protect 04000-07FFF (Disabled)
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75 | #pragma config WRT2 = OFF // Table Write Protect 08000-0BFFF (Disabled)
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76 | #pragma config WRT3 = OFF // Table Write Protect 0C000-0FFFF (Disabled)
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77 | #pragma config WRT4 = OFF // Table Write Protect 10000-13FFF (Disabled)
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78 | #pragma config WRT5 = OFF // Table Write Protect 14000-17FFF (Disabled)
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79 | #pragma config WRT6 = OFF // Table Write Protect 18000-1BFFF (Disabled)
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80 | #pragma config WRT7 = OFF // Table Write Protect 1C000-1FFFF (Disabled)
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81 |
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82 | // CONFIG6H
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83 | #pragma config WRTC = OFF // Config. Write Protect (Disabled)
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84 | #pragma config WRTB = OFF // Table Write Protect Boot (Disabled)
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85 | #pragma config WRTD = OFF // Data EE Write Protect (Disabled)
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86 |
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87 | // CONFIG7L
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88 | #pragma config EBRT0 = OFF // Table Read Protect 00800-03FFF (Disabled)
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89 | #pragma config EBRT1 = OFF // Table Read Protect 04000-07FFF (Disabled)
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90 | #pragma config EBRT2 = OFF // Table Read Protect 08000-0BFFF (Disabled)
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91 | #pragma config EBRT3 = OFF // Table Read Protect 0C000-0FFFF (Disabled)
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92 | #pragma config EBRT4 = OFF // Table Read Protect 10000-13FFF (Disabled)
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93 | #pragma config EBRT5 = OFF // Table Read Protect 14000-17FFF (Disabled)
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94 | #pragma config EBRT6 = OFF // Table Read Protect 18000-1BFFF (Disabled)
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95 | #pragma config EBRT7 = OFF // Table Read Protect 1C000-1FFFF (Disabled)
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96 |
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97 | // CONFIG7H
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98 | #pragma config EBRTB = OFF // Table Read Protect Boot (Disabled)
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99 |
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100 | /*** VARIABLES *********************************************************************************/
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101 |
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102 | #define _XTAL_FREQ 4000000 //Fosc frequency for _delay() library (4MHz)
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103 |
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104 | /*** PRIVATE PROTOTYPES ***********************************************************************/
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105 |
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106 | void Init(void); //Aufruf der Initialisierung vor Ausführung des main()
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107 |
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108 | //******************************************************************************
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109 | // MAIN PROGRAM
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110 | //******************************************************************************
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111 | void main(void)
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112 | {
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113 | Init(); //Initialisierung
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114 |
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115 | while(1) //Endlosschleife
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116 | {
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117 | }
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118 | }//end main();
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119 |
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120 | //*********************************************************************************************
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121 | // INITIALISIERUNG PIC
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122 | //*********************************************************************************************
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123 |
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124 | void Init(void)
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125 | {
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126 |
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127 | /*** SET VALUES OF VARIABLES ***********************************************************/
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128 |
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129 | /*** Set Inputs, Outputs ***************************************************************/
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130 | //*// All PINs with an * are free usable I/O PINs //*//
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131 |
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132 | //PORTA A0-A5
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133 | TRISAbits.TRISA0 = 1; //set RA0 as INPUT used for Taster 1
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134 | TRISAbits.TRISA1 = 1; //set RA1 as INPUT used for Taster 2
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135 | TRISAbits.TRISA2 = 1; //set RA2 as INPUT used for Taster 3
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136 | TRISAbits.TRISA3 = 1; //set RA3 as INPUT used for Taster 4
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137 | TRISAbits.TRISA4 = 1; //set RA4 as INPUT used for Taster 5
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138 | TRISAbits.TRISA5 = 1; //set RA5 as INPUT used for Schalter 1
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139 | //RA6 see the OSC2/CLKO/RA6 pin.
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140 | //RA7 see the OSC1/CLKI/RA7 pin.
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141 |
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142 |
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143 | //PORTB B0-B7
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144 | TRISBbits.TRISB0 = 0; //set RB0 as OUTPUT used as BT-mode
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145 | TRISBbits.TRISB6 = 1; //set RB6 as INPUT used as PGC
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146 | TRISBbits.TRISB7 = 1; //set RB7 as INPUT used as PGD
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147 |
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148 | //PORTC C0-C7
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149 | TRISCbits.TRISC6 = 0; //set RC6 as OUTPUT used as BT-UART TX
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150 | TRISCbits.TRISC7 = 1; //set RC7 as INPUT used as BT-UART RX
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151 |
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152 | //PORTG G0-G4
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153 | TRISGbits.TRISG4 = 0; //set RG4 as OUTPUT used for RTCC Pin
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154 | //RG5 used as MCLR
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155 |
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156 |
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157 |
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158 | RTCWREN = 1; //RTCC Value Registers Write Enable bit
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159 | //RTCVALH and RTCVALL registers can be written to by the user
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160 | RTCEN = 1; //RTCC module is enabled
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161 | RTCOE = 1; //RTCC clock output is enabled
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162 |
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163 | AMASK3 = 0; //Alarm Mask Configuration bits
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164 | AMASK2 = 0; //set to: Every 10 seconds
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165 | AMASK1 = 1;
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166 | AMASK0 = 0;
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167 |
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168 | ARPT7 = 0; // ALARM REPEAT REGISTER
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169 | ARPT6 = 0;
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170 | ARPT5 = 0;
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171 | ARPT4 = 1;
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172 | ARPT3 = 1;
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173 | ARPT2 = 1;
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174 | ARPT1 = 1;
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175 | ARPT0 = 1;
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176 |
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177 | }//end Initialization();
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178 | /*** end of file *********************************************************************************************/
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