1 | #include <msp430.h>
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2 | #include "stdint.h"
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3 | #include "stdbool.h"
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4 |
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5 | // Anaren AIR booster pack with LR09A (868/9xx MHz)
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6 | // CC110L
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7 | #define GDO2_BIT BIT0 // P1
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8 | #define SCLK_BIT BIT5 // P1
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9 | #define MISO_BIT BIT6 // P1
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10 | #define MOSI_BIT BIT7 // P1
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11 |
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12 | #define GDO0_BIT BIT6 // P2
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13 | #define CSN_BIT BIT7 // P2
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14 |
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15 | // 2553
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16 | //#define LEDrd_BIT BIT0 // P1
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17 | #define RX_BIT BIT1 // P1
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18 | #define TX_BIT BIT2 // P1
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19 | #define button_BIT BIT3 // P1
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20 | //#define LEDgn_BIT BIT6 // P1
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21 |
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22 | uint8_t status;
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23 | uint8_t test;
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24 |
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25 | uint8_t
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26 | softSPI(
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27 | uint8_t write
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28 | )
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29 | {
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30 | uint8_t read = 0;
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31 |
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32 | P1OUT &= ~(SCLK_BIT);
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33 |
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34 | uint8_t n;
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35 | for(n=8; n--;){
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36 |
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37 | // OUT
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38 | if (write & 1<<n){
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39 | P1OUT |= MOSI_BIT;
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40 | }
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41 | else{
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42 | P1OUT &= ~(MOSI_BIT);
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43 | }
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44 |
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45 | // CLOCK
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46 | P1OUT |= SCLK_BIT;
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47 |
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48 | // IN
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49 | if (P1IN & MISO_BIT){
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50 | read |= 1<<n;
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51 | }
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52 |
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53 | P1OUT &= ~(SCLK_BIT);
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54 | }
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55 |
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56 | return read;
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57 | }
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58 |
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59 | uint8_t
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60 | CC(
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61 | bool rw,
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62 | bool burst,
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63 | uint8_t address,
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64 | uint8_t data
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65 | )
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66 | {
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67 | uint8_t header =
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68 | (rw<<7) //
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69 | |(burst<<6) //
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70 | |(address & 0x3F) // 0x00 to 0x2E.
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71 | ;
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72 |
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73 | P2OUT &= ~(CSN_BIT);
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74 | while(P1IN & MISO_BIT);
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75 |
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76 | /*uint8_t*/ status = softSPI(header);
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77 | uint8_t read = softSPI(data);
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78 |
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79 | P2OUT |= CSN_BIT;
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80 |
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81 | return read;
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82 | }
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83 |
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84 | uint8_t CS(
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85 | bool rw,
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86 | uint8_t address
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87 | )
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88 | {
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89 | uint8_t header =
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90 | (rw<<7) //
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91 | //|(0<<6) //
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92 | |(address & 0x3D) // 0x30 through 0x3D).
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93 | ;
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94 |
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95 | P2OUT &= ~(CSN_BIT);
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96 | while(P1IN & MISO_BIT);
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97 |
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98 | uint8_t status = softSPI(header);
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99 |
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100 | P2OUT |= CSN_BIT;
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101 |
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102 | return status;
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103 | }
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104 |
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105 | int main(void) {
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106 |
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107 | // Stop watchdog timer
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108 | WDTCTL = WDTPW | WDTHOLD;
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109 |
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110 | BCSCTL1 = CALBC1_1MHZ;
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111 | DCOCTL = CALDCO_1MHZ;
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112 |
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113 | // serial
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114 | P1DIR = TX_BIT;
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115 | P2DIR = 0;
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116 |
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117 | // CC110x soft-SPI
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118 | P1DIR |= (MOSI_BIT | SCLK_BIT);
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119 |
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120 | P2OUT |= CSN_BIT;
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121 | P2DIR |= (CSN_BIT);
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122 | P2SEL &= ~(CSN_BIT);
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123 | P2SEL2 &= ~(CSN_BIT);
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124 |
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125 | // Manual Reset
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126 |
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127 | // Set SCLK = 1 and SI = 0.
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128 | P1OUT |= (SCLK_BIT);
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129 | P1OUT &= ~(MOSI_BIT);
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130 |
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131 | // Strobe CSn low / high.
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132 | //P2OUT &= ~(CSN_BIT);
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133 | //P2OUT |= CSN_BIT;
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134 | // Hold CSn low and then high for at least 40 µs relative to pulling CSn low
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135 | P2OUT &= ~(CSN_BIT);
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136 | P2OUT |= CSN_BIT;
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137 | uint8_t n;
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138 | for(n=10; n; n--);
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139 |
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140 | // Pull CSn low and wait for SO to go low ( CHIP_RDYn).
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141 | P2OUT &= ~(CSN_BIT);
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142 | while(P1IN & MISO_BIT);
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143 |
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144 | // Issue the SRES strobe on the SI line.
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145 | CS(0, 0x30); // Reset
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146 |
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147 | CS(0, 0x30); // Reset
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148 |
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149 | CS(0, 0x30); // Reset
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150 |
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151 | // When SO goes low again, reset is complete and the chip is in the IDLE state.
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152 |
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153 | CS(0, 0x3D); // NOP, TX FIFO free
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154 | CS(1, 0x3D); // NOP, RX FIFO bytes
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155 |
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156 | CC(true, true, 0x30, 0); // chip
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157 | CC(true, true, 0x31, 0); // version
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158 |
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159 | CS(1, 0x3A); // flush RX FIFO
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160 | CS(1, 0x3B); // flush TX FIFO
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161 |
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162 | //PATABLE
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163 | P2OUT &= ~(CSN_BIT);
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164 | while(P1IN & MISO_BIT);
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165 | softSPI( (0<<7)|(1<<6)|0x3E );
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166 | softSPI(0x00);
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167 | softSPI(0x50);
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168 | P2OUT |= CSN_BIT;
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169 |
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170 |
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171 | P2OUT &= ~(CSN_BIT);
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172 | while(P1IN & MISO_BIT);
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173 | softSPI( (1<<7)|(1<<6)|0x3E );
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174 | softSPI( (1<<7)|0x00);
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175 | softSPI( (1<<7)|0x00);
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176 | P2OUT |= CSN_BIT;
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177 |
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178 |
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179 |
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180 | // Rf settings for CC110L
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181 | CC(false, false, 0x0000, 0x29); // IOCFG2 GDO2 Output Pin Configuration
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182 | CC(false, false, 0x0001, 0x2E); // IOCFG1 GDO1 Output Pin Configuration
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183 | CC(false, false, 0x0002, 0x06); // IOCFG0 GDO0 Output Pin Configuration
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184 | CC(false, false, 0x0003, 0x47); // FIFOTHR RX FIFO and TX FIFO Thresholds
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185 | CC(false, false, 0x0004, 0xD3); // SYNC1 Sync Word, High Byte
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186 | CC(false, false, 0x0005, 0x91); // SYNC0 Sync Word, Low Byte
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187 | CC(false, false, 0x0006, 0x01); // PKTLEN Packet Length
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188 | CC(false, false, 0x0007, 0x00); // PKTCTRL1 Packet Automation Control
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189 | CC(false, false, 0x0008, 0x00); // PKTCTRL0 Packet Automation Control
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190 | CC(false, false, 0x0009, 0x00); // ADDR Device Address
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191 | CC(false, false, 0x000A, 0x00); // CHANNR Channel number
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192 | CC(false, false, 0x000B, 0x06); // FSCTRL1 Frequency Synthesizer Control
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193 | CC(false, false, 0x000C, 0x00); // FSCTRL0 Frequency Synthesizer Control
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194 | CC(false, false, 0x000D, 0x20); // FREQ2 Frequency Control Word, High Byte
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195 | CC(false, false, 0x000E, 0x28); // FREQ1 Frequency Control Word, Middle Byte
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196 | CC(false, false, 0x000F, 0xC5); // FREQ0 Frequency Control Word, Low Byte
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197 | CC(false, false, 0x0010, 0xF6); // MDMCFG4 Modem Configuration
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198 | CC(false, false, 0x0011, 0x84); // MDMCFG3 Modem Configuration
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199 | CC(false, false, 0x0012, 0x30); // MDMCFG2 Modem Configuration
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200 | CC(false, false, 0x0013, 0x22); // MDMCFG1 Modem Configuration
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201 | CC(false, false, 0x0014, 0xE5); // MDMCFG0 Modem Configuration
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202 | CC(false, false, 0x0015, 0x14); // DEVIATN Modem Deviation Setting
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203 | CC(false, false, 0x0016, 0x07); // MCSM2 Main Radio Control State Machine Configuration
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204 | CC(false, false, 0x0017, 0x30); // MCSM1 Main Radio Control State Machine Configuration
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205 | CC(false, false, 0x0018, 0x18); // MCSM0 Main Radio Control State Machine Configuration
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206 | CC(false, false, 0x0019, 0x16); // FOCCFG Frequency Offset Compensation Configuration
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207 | CC(false, false, 0x001A, 0x6C); // BSCFG Bit Synchronization Configuration
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208 | CC(false, false, 0x001B, 0x03); // AGCCTRL2 AGC Control
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209 | CC(false, false, 0x001C, 0x40); // AGCCTRL1 AGC Control
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210 | CC(false, false, 0x001D, 0x91); // AGCCTRL0 AGC Control
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211 | CC(false, false, 0x0020, 0xFB); // RESERVED_0X20 Use setting from SmartRF Studio
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212 | CC(false, false, 0x0021, 0x56); // FREND1 Front End RX Configuration
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213 | CC(false, false, 0x0022, 0x11); // FREND0 Front End TX Configuration
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214 | CC(false, false, 0x0023, 0xE9); // FSCAL3 Frequency Synthesizer Calibration
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215 | CC(false, false, 0x0024, 0x2A); // FSCAL2 Frequency Synthesizer Calibration
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216 | CC(false, false, 0x0025, 0x00); // FSCAL1 Frequency Synthesizer Calibration
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217 | CC(false, false, 0x0026, 0x1F); // FSCAL0 Frequency Synthesizer Calibration
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218 | CC(false, false, 0x0029, 0x89); // RESERVED_0X29 Use setting from SmartRF Studio
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219 | CC(false, false, 0x002A, 0x127); // RESERVED_0X2A Use setting from SmartRF Studio
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220 | CC(false, false, 0x002B, 0x63); // RESERVED_0X2B Use setting from SmartRF Studio
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221 | CC(false, false, 0x002C, 0x81); // TEST2 Various Test Settings
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222 | CC(false, false, 0x002D, 0x35); // TEST1 Various Test Settings
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223 | CC(false, false, 0x002E, 0x09); // TEST0 Various Test Settings
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224 |
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225 | test = CC(false, false, 0x3F, 0xB1);
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226 |
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227 | CS(0, 0x35); // TX strobe
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228 |
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229 | for(;;)
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230 | CS(0, 0x3D); // NOP, TX FIFO free
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231 |
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232 | LPM0;
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233 | for(;;);
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234 | }
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