1 | PORTD_DIR = 0xFF;
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2 | PORTB_DIR = 0xFF;
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3 | PORTC_DIR = 0xFF;
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4 | PORTC_OUT = 0;
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5 | TCC1_CTRLA = TC_CLKSEL_DIV1_gc;
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6 | TCC1_PERBUF = 256;
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7 | //TCC1_INTCTRLA = 0x02;
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8 |
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9 | DMA.CH0.CTRLA = DMA_CH_SINGLE_bm | DMA_CH_BURSTLEN_2BYTE_gc; //DMA Block macht bei jedem Trigger 2 Byte (signle)
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10 | DMA.CH0.CTRLB = 0x03; //Interrupt mit höchster Priorität
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11 | DMA.CH0.ADDRCTRL = DMA_CH_SRCRELOAD_BLOCK_gc; //Nach jedem Block die Quelladresse reseten
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12 | DMA.CH0.ADDRCTRL |= DMA_CH_DESTDIR_INC_gc; //Quelladresse immer +1
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13 | DMA.CH0.ADDRCTRL |= DMA_CH_DESTRELOAD_BURST_gc; //Zieladresse nach jedem Burst (2Byte) neu laden
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14 | DMA.CH0.ADDRCTRL |= DMA_CH_DESTDIR_FIXED_gc; //Zieladresse ist FIX
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15 | DMA.CH0.TRIGSRC = DMA_CH_TRIGSRC_TCC1_OVF_gc; //Triggerevtn ist Timer TCC1 overflow
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16 | DMA.CH0.TRFCNT = BUFFER_SIZE*2; //buffer_SIZE*2 Bytes
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17 | DMA.CH0.REPCNT = 1; //0 WIederholungen - nach 1 Block ist Transaction fertig
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18 | DMA.CH0.SRCADDR0 = (DWORD)&DMA_Buffer1 & 0xFF;
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19 | DMA.CH0.SRCADDR1 = ((DWORD)&DMA_Buffer1>>8) & 0xFF;
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20 | DMA.CH0.SRCADDR2 = ((DWORD)&DMA_Buffer1>>16) & 0xFF;
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21 | DMA.CH0.DESTADDR0 = (DWORD)&DACB.CH0DATA & 0xFF;
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22 | DMA.CH0.DESTADDR1 = ((DWORD)&DACB.CH0DATA>>8) & 0xFF;
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23 | DMA.CH0.DESTADDR2 = ((DWORD)&DACB.CH0DATA>>16) & 0xFF;
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24 |
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25 | DMA.CH1.CTRLA = DMA_CH_SINGLE_bm | DMA_CH_BURSTLEN_2BYTE_gc; //DMA Block macht bei jedem Trigger 2 Byte (signle)
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26 | DMA.CH1.CTRLB = 0x03; //Interrupt mit höchster Priorität
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27 | DMA.CH1.ADDRCTRL = DMA_CH_SRCRELOAD_BLOCK_gc; //Nach jedem Block die Quelladresse reseten
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28 | DMA.CH1.ADDRCTRL |= DMA_CH_DESTDIR_INC_gc; //Quelladresse immer +1
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29 | DMA.CH1.ADDRCTRL |= DMA_CH_DESTRELOAD_BURST_gc; //Zieladresse nach jedem Burst (2Byte) neu laden
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30 | DMA.CH1.ADDRCTRL |= DMA_CH_DESTDIR_FIXED_gc; //Zieladresse ist FIX
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31 | DMA.CH1.TRIGSRC = DMA_CH_TRIGSRC_TCC1_OVF_gc; //Triggerevtn ist Timer TCC1 overflow
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32 | DMA.CH1.TRFCNT = BUFFER_SIZE*2; //buffer_SIZE*2 Bytes
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33 | DMA.CH1.REPCNT = 1; //0 WIederholungen - nach 1 Block ist Transaction fertig
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34 | DMA.CH1.SRCADDR0 = (DWORD)&DMA_Buffer2 & 0xFF;
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35 | DMA.CH1.SRCADDR1 = ((DWORD)&DMA_Buffer2>>8) & 0xFF;
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36 | DMA.CH1.SRCADDR2 = ((DWORD)&DMA_Buffer2>>16) & 0xFF;
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37 | DMA.CH1.DESTADDR0 = (DWORD)&DACB.CH0DATA & 0xFF;
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38 | DMA.CH1.DESTADDR1 = ((DWORD)&DACB.CH0DATA>>8) & 0xFF;
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39 | DMA.CH1.DESTADDR2 = ((DWORD)&DACB.CH0DATA>>16) & 0xFF;
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40 |
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41 | DMA.CTRL = DMA_ENABLE_bm | DMA_DBUFMODE_CH01_gc;
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42 | DMA.CH0.CTRLA |= DMA_CH_ENABLE_bm;
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43 |
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44 | DACB.CTRLA = DAC_CH1EN_bm | DAC_CH0EN_bm | DAC_ENABLE_bm; //Alle kanäle vom DAC aktivieren
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45 | DACB.CTRLB = DAC_CHSEL_DUAL_gc; //Kanäle getrennt steuern
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46 | DACB.CTRLC = DAC_REFSEL_AVCC_gc; //VCC als Referenzspannung
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