Für meine Experimente mit dem Nucleo STM32F767ZI habe ich auf https://github.com/FBergemann/STM32-FreeRTOS-Framework/tree/master den TIM5 mit IRQ und PWM aktiviert. Da ich noch kein Oszilloskop habe, zähle ich die Timer-Zyklen im IRQ, während ich die PWM Parameter über eine Tabelle ändere (https://github.com/FBergemann/STM32-FreeRTOS-Framework/blob/master/User/UserSrc/Tasks/TaskPWM/TaskPWM.c). TIM5 liegt auf APB2. Der wird mit 168 MHz versorgt. Der initiale Prescaler Wert ist 2688 -> 62500 Hz. Die initiale Counter Period ist 31250 -> 0.5 Hz (?!) Aber mit dem Setting habe ich #1 Interrupt pro Sekunde (nicht 0.5) - warum? Und wenn ich dann in einer Tabelle (in TaskPWM.c) über die Zeit die Frequenz hochschraube, dann komme ich nur bis ca 220 KHz. Bei höherer Frequenz hängt es sich auf. Ich vermute, es liegt daran, dass irgendwann die Interrupt Routine nicht mehr hinterher kommt. Auch wenn meine Routine nur einen 32 bit counter hochzählt, wird mir das HAL wieder einiges mehr auferlegen. Ist es wirklich die Ausführungsdauer der Interrupt Routine, die hier limitiert? Kann man das irgendwie grob berechnen? Z.B. 168000000 / 220000 = 764 CPU Takte Zeit für die Interrupt-Routine - und was sonst noch alles unter FreeRTOS läuft - bei 220000 Hz?
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Ich vermute mal, dass die Lösung in einer timer-chain liegt. Dann kann ein zweiter Timer die Zyklen des ersten Timers zählen - ohne dass ich dafür einen Interrupt benötige. Und dessen CNT kann direkt ausgelesen werden. Da ich TIM5 verwende, müsste z.B. TIM3 über ITR2 als Slave gehen. Bei 1MHz für TIM5 läuft der 16 Bit TIM3 allerdings pro Sekunde schon 15,24 mal durch. Und ich habe im Datenblatt keine Option gesehen, um TIM2 (32 bit) als Slave für TIM5 zu verwenden(?) Also muss ich vermutlich nach dem TIM3 noch den TIM4 hängen, um höhere Frequenz durch einen Slave zählen zu lassen(?) Aber erst mal zurück zu dem einen Slave TIM3. Aus irgendeinem Grund ist mein TIM3->CNT immer noch dauerhaft #0. Habe ich bei der Timer-Konfiguration etwas falsch gemacht? https://github.com/FBergemann/STM32-FreeRTOS-Framework/blob/dev-pwm/Core/Src/main.c (-> MX_TIM3_Init(void), MX_TIM5_Init(void))
Also langsam bekomme ich einen Föhn: https://community.st.com/s/question/0D50X00009sWbv9SAC/masterslave-problem-on-tim3-in-stm32l476-slave-not-counting-when-itr2-selected
what a mess... Mit TIM2 -> TIM5 (master -> slave) funktioniert es:
1 | 2021-05-01 00:00:00.005:CON:start TaskConsole... |
2 | 2021-05-01 00:00:00.005:L1 :start Task1... |
3 | 2021-05-01 00:00:00.005:L3 :start Task3... |
4 | 2021-05-01 00:00:00.104:PWM:start TaskPWM... |
5 | 2021-05-01 00:00:00.104:PWM:TIM2 pulses/sec = #0000000000, TIM5 ctr = #0000000000 |
6 | 2021-05-01 00:00:01.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000001 |
7 | 2021-05-01 00:00:02.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000002 |
8 | 2021-05-01 00:00:03.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000003 |
9 | 2021-05-01 00:00:04.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000004 |
10 | 2021-05-01 00:00:05.104:PWM:TIM2 pulses/sec = #0000000002, TIM5 ctr = #0000000006 |
11 | 2021-05-01 00:00:06.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000016 |
12 | 2021-05-01 00:00:07.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000026 |
13 | 2021-05-01 00:00:08.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000036 |
14 | 2021-05-01 00:00:09.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000046 |
15 | 2021-05-01 00:00:10.104:PWM:TIM2 pulses/sec = #0000000091, TIM5 ctr = #0000000137 |
16 | 2021-05-01 00:00:11.104:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000236 |
17 | 2021-05-01 00:00:12.104:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000336 |
18 | 2021-05-01 00:00:13.104:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000436 |
19 | 2021-05-01 00:00:14.104:PWM:TIM2 pulses/sec = #0000000099, TIM5 ctr = #0000000536 |
20 | 2021-05-01 00:00:15.104:PWM:TIM2 pulses/sec = #0000000972, TIM5 ctr = #0000001507 |
21 | 2021-05-01 00:00:16.104:PWM:TIM2 pulses/sec = #0000000976, TIM5 ctr = #0000002484 |
22 | 2021-05-01 00:00:17.104:PWM:TIM2 pulses/sec = #0000000977, TIM5 ctr = #0000003460 |
23 | 2021-05-01 00:00:18.104:PWM:TIM2 pulses/sec = #0000000976, TIM5 ctr = #0000004437 |
24 | 2021-05-01 00:00:19.104:PWM:TIM2 pulses/sec = #0000000977, TIM5 ctr = #0000005413 |
25 | 2021-05-01 00:00:20.104:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000006725 |
26 | 2021-05-01 00:00:21.104:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000008037 |
27 | 2021-05-01 00:00:22.104:PWM:TIM2 pulses/sec = #0000001311, TIM5 ctr = #0000009349 |
28 | 2021-05-01 00:00:23.104:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000010661 |
29 | 2021-05-01 00:00:24.104:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000011973 |
30 | 2021-05-01 00:00:25.104:PWM:TIM2 pulses/sec = #0000025971, TIM5 ctr = #0000037944 |
31 | 2021-05-01 00:00:26.104:PWM:TIM2 pulses/sec = #0000025991, TIM5 ctr = #0000063934 |
32 | 2021-05-01 00:00:27.104:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000024388 |
33 | 2021-05-01 00:00:28.104:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000050378 |
34 | 2021-05-01 00:00:29.104:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000010833 |
35 | 2021-05-01 00:00:30.104:PWM:TIM2 pulses/sec = #0000124991, TIM5 ctr = #0000004762 |
36 | 2021-05-01 00:00:31.104:PWM:TIM2 pulses/sec = #0000124991, TIM5 ctr = #0000064226 |
37 | 2021-05-01 00:00:32.104:PWM:TIM2 pulses/sec = #0000124991, TIM5 ctr = #0000058154 |
38 | 2021-05-01 00:00:33.104:PWM:TIM2 pulses/sec = #0000124991, TIM5 ctr = #0000052082 |
39 | 2021-05-01 00:00:34.104:PWM:TIM2 pulses/sec = #0000124991, TIM5 ctr = #0000046012 |
40 | 2021-05-01 00:00:35.104:PWM:TIM2 pulses/sec = #0000219909, TIM5 ctr = #0000006113 |
41 | 2021-05-01 00:00:36.104:PWM:TIM2 pulses/sec = #0000219896, TIM5 ctr = #0000031728 |
42 | 2021-05-01 00:00:37.104:PWM:TIM2 pulses/sec = #0000219888, TIM5 ctr = #0000057341 |
43 | 2021-05-01 00:00:38.104:PWM:TIM2 pulses/sec = #0000219893, TIM5 ctr = #0000017419 |
44 | 2021-05-01 00:00:39.104:PWM:TIM2 pulses/sec = #0000219882, TIM5 ctr = #0000043020 |
45 | 2021-05-01 00:00:40.104:PWM:TIM2 pulses/sec = #0000000006, TIM5 ctr = #0000043021 |
46 | 2021-05-01 00:00:41.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000043022 |
47 | 2021-05-01 00:00:42.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000043023 |
48 | 2021-05-01 00:00:43.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000043024 |
49 | 2021-05-01 00:00:44.104:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000043025 |
50 | 2021-05-01 00:00:45.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000043035 |
51 | 2021-05-01 00:00:46.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000043045 |
52 | 2021-05-01 00:00:47.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000043055 |
53 | 2021-05-01 00:00:48.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000043065 |
54 | 2021-05-01 00:00:49.104:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000043075 |
naja, noch nicht so ganz...
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Offensichtlich macht der TIM5 einen wrap-around bei 16 bit (65535). Wo kommt das denn jetzt her? Ich denke, TIM5 ist ein 32 bit timer?
Der Fehler sitzt vor dem Bildschirm. Ich habe verwendet:
1 | LogUInt16ToStr(sBuff + 43, copyCounterTIM5, 10); |
anstelle von
1 | LogUInt32ToStr(sBuff + 43, copyCounterTIM5, 10); |
1 | 2021-05-01 00:00:00.003:CON:start TaskConsole... |
2 | 2021-05-01 00:00:00.004:L1 :start Task1... |
3 | 2021-05-01 00:00:00.004:L3 :start Task3... |
4 | 2021-05-01 00:00:00.102:PWM:start TaskPWM... |
5 | 2021-05-01 00:00:00.103:PWM:TIM2 pulses/sec = #0000000000, TIM5 ctr = #0000000000 |
6 | 2021-05-01 00:00:01.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000001 |
7 | 2021-05-01 00:00:02.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000002 |
8 | 2021-05-01 00:00:03.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000003 |
9 | 2021-05-01 00:00:04.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0000000004 |
10 | 2021-05-01 00:00:05.102:PWM:TIM2 pulses/sec = #0000000002, TIM5 ctr = #0000000006 |
11 | 2021-05-01 00:00:06.102:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000016 |
12 | 2021-05-01 00:00:07.102:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000026 |
13 | 2021-05-01 00:00:08.102:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000036 |
14 | 2021-05-01 00:00:09.102:PWM:TIM2 pulses/sec = #0000000010, TIM5 ctr = #0000000046 |
15 | 2021-05-01 00:00:10.102:PWM:TIM2 pulses/sec = #0000000091, TIM5 ctr = #0000000136 |
16 | 2021-05-01 00:00:11.102:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000236 |
17 | 2021-05-01 00:00:12.102:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000336 |
18 | 2021-05-01 00:00:13.102:PWM:TIM2 pulses/sec = #0000000099, TIM5 ctr = #0000000436 |
19 | 2021-05-01 00:00:14.102:PWM:TIM2 pulses/sec = #0000000100, TIM5 ctr = #0000000536 |
20 | 2021-05-01 00:00:15.102:PWM:TIM2 pulses/sec = #0000000970, TIM5 ctr = #0000001506 |
21 | 2021-05-01 00:00:16.102:PWM:TIM2 pulses/sec = #0000000977, TIM5 ctr = #0000002482 |
22 | 2021-05-01 00:00:17.102:PWM:TIM2 pulses/sec = #0000000976, TIM5 ctr = #0000003459 |
23 | 2021-05-01 00:00:18.102:PWM:TIM2 pulses/sec = #0000000977, TIM5 ctr = #0000004435 |
24 | 2021-05-01 00:00:19.102:PWM:TIM2 pulses/sec = #0000000977, TIM5 ctr = #0000005412 |
25 | 2021-05-01 00:00:20.102:PWM:TIM2 pulses/sec = #0000001311, TIM5 ctr = #0000006724 |
26 | 2021-05-01 00:00:21.102:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000008036 |
27 | 2021-05-01 00:00:22.102:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000009347 |
28 | 2021-05-01 00:00:23.102:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000010659 |
29 | 2021-05-01 00:00:24.102:PWM:TIM2 pulses/sec = #0000001312, TIM5 ctr = #0000011971 |
30 | 2021-05-01 00:00:25.102:PWM:TIM2 pulses/sec = #0000025982, TIM5 ctr = #0000037954 |
31 | 2021-05-01 00:00:26.102:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000063944 |
32 | 2021-05-01 00:00:27.102:PWM:TIM2 pulses/sec = #0000025991, TIM5 ctr = #0000089934 |
33 | 2021-05-01 00:00:28.102:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000115924 |
34 | 2021-05-01 00:00:29.102:PWM:TIM2 pulses/sec = #0000025990, TIM5 ctr = #0000141914 |
35 | 2021-05-01 00:00:30.102:PWM:TIM2 pulses/sec = #0000124998, TIM5 ctr = #0000266915 |
36 | 2021-05-01 00:00:31.102:PWM:TIM2 pulses/sec = #0000124998, TIM5 ctr = #0000391915 |
37 | 2021-05-01 00:00:32.102:PWM:TIM2 pulses/sec = #0000124998, TIM5 ctr = #0000516915 |
38 | 2021-05-01 00:00:33.102:PWM:TIM2 pulses/sec = #0000124998, TIM5 ctr = #0000641915 |
39 | 2021-05-01 00:00:34.103:PWM:TIM2 pulses/sec = #0000124998, TIM5 ctr = #0000766915 |
40 | 2021-05-01 00:00:35.103:PWM:TIM2 pulses/sec = #0000219793, TIM5 ctr = #0000989144 |
41 | 2021-05-01 00:00:36.103:PWM:TIM2 pulses/sec = #0000219722, TIM5 ctr = #0001211367 |
42 | 2021-05-01 00:00:37.103:PWM:TIM2 pulses/sec = #0000219679, TIM5 ctr = #0001433589 |
43 | 2021-05-01 00:00:38.103:PWM:TIM2 pulses/sec = #0000219726, TIM5 ctr = #0001655812 |
44 | 2021-05-01 00:00:39.103:PWM:TIM2 pulses/sec = #0000219739, TIM5 ctr = #0001878033 |
45 | 2021-05-01 00:00:40.102:PWM:TIM2 pulses/sec = #0000000007, TIM5 ctr = #0001878039 |
46 | 2021-05-01 00:00:41.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0001878040 |
47 | 2021-05-01 00:00:42.102:PWM:TIM2 pulses/sec = #0000000001, TIM5 ctr = #0001878041 |
:-)
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