Forum: Mikrocontroller und Digitale Elektronik Infineon XMC4700 mit OpenBLT und FreeRTOS Problem


Infineon XMC4700 mit OpenBLT und FreeRTOS Problem
von Lukas W. (lukas_we)

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Hallo,

ich habe das Problem das ich es nicht schaffe das meinen XMC4700 mit dem 
Bootloader OpenBLT ein Dave CE Projekt mit FreeRTOS zu starten. Ich 
hatte das ganze Projekt schonmal soweit das es wenigstens schonmal etwas 
in der Main ausgeführt hatte. Jedoch ist, nach vielen versuchen das 
ganze Projekt zum laufen zu bekommen, alles nur noch gecrasht und und 
ich habe das Projekt neu aufsetzten müssen. Jetzt bleibt das Programm 
irgendwo in der irgendwo im Startup hängen aber ich weiß nicht wieso. 
Der Bootloader läuft ohne Probleme und spielt das Programm in den Flash. 
Das ganze habe ich mit dem mitgelieferten Beispielprogramm, welches eine 
LED blinken lässt, getestet.

Hier ein paar daten zu meinem Projekt:

Evalboard: KIT_XMC47_RELAX_V1 
https://www.infineon.com/cms/de/product/evaluation-boards/kit_xmc47_relax_v1/

IDE: DAVE 4
Bootloader: OpenBLT https://github.com/feaser/openblt
RTOS: FreeRTOS

Linker Skript Bootloader:

1
OUTPUT_FORMAT("elf32-littlearm")

2
OUTPUT_ARCH(arm)

3
ENTRY(Reset_Handler)

4
5
stack_size = DEFINED(stack_size) ? stack_size : 2048;

6
no_init_size = 64;

7
8
MEMORY

9
{

10
  FLASH_1_cached(RX) : ORIGIN = 0x08000000, LENGTH = 0xC000

11
  FLASH_1_uncached(RX) : ORIGIN = 0x0C000000, LENGTH = 0xC000

12
  PSRAM_1(!RX) : ORIGIN = 0x1FFE8040, LENGTH = 0x17fc0

13
  DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000

14
  DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000

15
  SRAM_combined(!RX) : ORIGIN = 0x1FFE8040, LENGTH = 0x57fc0

16
  SHARED(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x40

17
}

18
19
SECTIONS

20
{

21
    /* Shared data section that also shouldn't get zeroed */

22
    .shared (NOLOAD) :

23
    {

24
        . = ALIGN(4);

25
        _sshared = .;         /* define a global symbol at shared start */

26
        __shared_start__ = _sshared;

27
        *(.shared)

28
        *(.shared.*)

29
        KEEP(*(.shared)) 

30
        . = ALIGN(4);

31
        _eshared = .;         /* define a global symbol at shared end */

32
        __shared_end__ = _eshared;

33
    } >SHARED

34
35
    /* TEXT section */

36
37
    .text :

38
    {

39
        sText = .;

40
        KEEP(*(.reset));

41
        *(.text .text.* .gnu.linkonce.t.*);

42
43
        /* C++ Support */

44
        KEEP(*(.init))

45
        KEEP(*(.fini))

46
47
        /* .ctors */

48
        *crtbegin.o(.ctors)

49
        *crtbegin?.o(.ctors)

50
        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

51
        *(SORT(.ctors.*))

52
        *(.ctors)

53
54
        /* .dtors */

55
        *crtbegin.o(.dtors)

56
        *crtbegin?.o(.dtors)

57
        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

58
        *(SORT(.dtors.*))

59
        *(.dtors)

60
61
        *(.rodata .rodata.*)

62
        *(.gnu.linkonce.r*)

63
        

64
        *(vtable)        

65
        . = ALIGN(4);        

66
    } > FLASH_1_cached AT > FLASH_1_uncached

67
68
    .eh_frame_hdr : ALIGN (4)

69
    {

70
      KEEP (*(.eh_frame_hdr))

71
    } > FLASH_1_cached AT > FLASH_1_uncached

72
  

73
    .eh_frame : ALIGN (4)

74
    {

75
      KEEP (*(.eh_frame))

76
    } > FLASH_1_cached AT > FLASH_1_uncached

77
78
    /* Exception handling, exidx needs a dedicated section */

79
    .ARM.extab : ALIGN(4)

80
    {

81
        *(.ARM.extab* .gnu.linkonce.armextab.*)

82
    } > FLASH_1_cached AT > FLASH_1_uncached

83
84
    . = ALIGN(4);

85
    __exidx_start = .;

86
    .ARM.exidx : ALIGN(4)

87
    {

88
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

89
    } > FLASH_1_cached AT > FLASH_1_uncached

90
    __exidx_end = .;

91
    . = ALIGN(4);

92
    

93
    /* DSRAM layout (Lowest to highest)*/

94
    Stack (NOLOAD) : 

95
    {

96
        __stack_start = .;

97
        . = . + stack_size;

98
        __stack_end = .;

99
        __initial_sp = .;

100
    } > SRAM_combined

101
102
    /* functions with __attribute__((section(".ram_code"))) */

103
    .ram_code :

104
    {

105
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

106
        __ram_code_start = .;

107
        *(.ram_code)

108
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

109
        __ram_code_end = .;

110
    } > SRAM_combined AT > FLASH_1_uncached

111
    __ram_code_load = LOADADDR (.ram_code);

112
    __ram_code_size = __ram_code_end - __ram_code_start;

113
114
    /* Standard DATA and user defined DATA/BSS/CONST sections */

115
    .data :

116
    {

117
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

118
        __data_start = .;

119
        * (.data);

120
        * (.data*);

121
        *(*.data);

122
        *(.gnu.linkonce.d*)

123
      

124
        . = ALIGN(4);

125
        /* preinit data */

126
        PROVIDE_HIDDEN (__preinit_array_start = .);

127
        KEEP(*(.preinit_array))

128
        PROVIDE_HIDDEN (__preinit_array_end = .);

129
130
        . = ALIGN(4);

131
        /* init data */

132
        PROVIDE_HIDDEN (__init_array_start = .);

133
        KEEP(*(SORT(.init_array.*)))

134
        KEEP(*(.init_array))

135
        PROVIDE_HIDDEN (__init_array_end = .);

136
137
        . = ALIGN(4);

138
        /* finit data */

139
        PROVIDE_HIDDEN (__fini_array_start = .);

140
        KEEP(*(SORT(.fini_array.*)))

141
        KEEP(*(.fini_array))

142
        PROVIDE_HIDDEN (__fini_array_end = .);

143
144
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

145
        __data_end = .;

146
    } > SRAM_combined AT > FLASH_1_uncached

147
    __data_load = LOADADDR (.data);

148
    __data_size = __data_end - __data_start;

149
        

150
    __text_size = (__exidx_end - sText) + __data_size + __ram_code_size;

151
    eText = sText + __text_size;

152
153
    /* BSS section */

154
    .bss (NOLOAD) : 

155
    {

156
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

157
        __bss_start = .;

158
        * (.bss);

159
        * (.bss*);

160
        * (COMMON);

161
        *(.gnu.linkonce.b*)

162
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

163
        __bss_end = .;

164
    } > SRAM_combined

165
    __bss_size = __bss_end - __bss_start;

166
167
    /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */    

168
    __shift_loc =  (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end);

169
170
    USB_RAM  (__bss_end + __shift_loc) (NOLOAD) :

171
    {

172
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

173
        USB_RAM_start = .;

174
        *(USB_RAM)

175
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

176
        USB_RAM_end = .;

177
    } > SRAM_combined

178
    USB_RAM_size = USB_RAM_end - USB_RAM_start;

179
180
    ETH_RAM (USB_RAM_end) (NOLOAD) :

181
    {

182
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

183
        ETH_RAM_start = .;

184
        *(ETH_RAM)

185
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

186
        ETH_RAM_end = .;

187
        . = ALIGN(8);

188
        Heap_Bank1_Start = .;

189
    } > SRAM_combined

190
    ETH_RAM_size = ETH_RAM_end - ETH_RAM_start;

191
192
    /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/

193
    .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : 

194
    {

195
        Heap_Bank1_End = .;

196
        * (.no_init);

197
    } > SRAM_combined

198
199
    /* Heap - Bank1*/

200
    Heap_Bank1_Size  = Heap_Bank1_End - Heap_Bank1_Start;

201
202
    ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")

203
204
    /DISCARD/ :

205
    {

206
        *(.comment)

207
    }

208
209
    .stab       0 (NOLOAD) : { *(.stab) }

210
    .stabstr    0 (NOLOAD) : { *(.stabstr) }

211
212
    /* DWARF 1 */

213
    .debug              0 : { *(.debug) }

214
    .line               0 : { *(.line) }

215
216
    /* GNU DWARF 1 extensions */

217
    .debug_srcinfo      0 : { *(.debug_srcinfo) }

218
    .debug_sfnames      0 : { *(.debug_sfnames) }

219
220
    /* DWARF 1.1 and DWARF 2 */

221
    .debug_aranges      0 : { *(.debug_aranges) }

222
    .debug_pubnames     0 : { *(.debug_pubnames) }

223
    .debug_pubtypes     0 : { *(.debug_pubtypes) }

224
225
    /* DWARF 2 */

226
    .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }

227
    .debug_abbrev       0 : { *(.debug_abbrev) }

228
    .debug_line         0 : { *(.debug_line) }

229
    .debug_frame        0 : { *(.debug_frame) }

230
    .debug_str          0 : { *(.debug_str) }

231
    .debug_loc          0 : { *(.debug_loc) }

232
    .debug_macinfo      0 : { *(.debug_macinfo) }

233
234
    /* DWARF 2.1 */

235
    .debug_ranges       0 : { *(.debug_ranges) }

236
237
    /* SGI/MIPS DWARF 2 extensions */

238
    .debug_weaknames    0 : { *(.debug_weaknames) }

239
    .debug_funcnames    0 : { *(.debug_funcnames) }

240
    .debug_typenames    0 : { *(.debug_typenames) }

241
    .debug_varnames     0 : { *(.debug_varnames) }

242
243
    /* Build attributes */

244
    .build_attributes   0 : { *(.ARM.attributes) }

245
}


Linker Skript Programm:

1
OUTPUT_FORMAT("elf32-littlearm")

2
OUTPUT_ARCH(arm)

3
ENTRY(Reset_Handler)

4
5
stack_size = DEFINED(stack_size) ? stack_size : 2048;

6
no_init_size = 64;

7
8
MEMORY

9
{

10
    FLASH_1_cached(RX) : ORIGIN = 0x0800C000, LENGTH = 0x1f4000

11
    FLASH_1_uncached(RX) : ORIGIN = 0x0C00C000, LENGTH = 0x1f4000

12
    PSRAM_1(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x18000

13
    DSRAM_1_system(!RX) : ORIGIN = 0x20000000, LENGTH = 0x20000

14
    DSRAM_2_comm(!RX) : ORIGIN = 0x20020000, LENGTH = 0x20000

15
    SRAM_combined(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x00058000

16
    SHARED(!RX) : ORIGIN = 0x1FFE8000, LENGTH = 0x40

17
}

18
19
SECTIONS

20
{

21
    /* Shared data section that also shouldn't get zeroed */

22
    .shared (NOLOAD) :

23
    {

24
        . = ALIGN(4);

25
        _sshared = .;         /* define a global symbol at shared start */

26
        __shared_start__ = _sshared;

27
        *(.shared)

28
        *(.shared.*)

29
        KEEP(*(.shared)) 

30
        . = ALIGN(4);

31
        _eshared = .;         /* define a global symbol at shared end */

32
        __shared_end__ = _eshared;

33
    } >SHARED

34
    

35
    /* TEXT section */

36
37
    .text :

38
    {

39
        sText = .;

40
        KEEP(*(.reset));

41
        *(.text .text.* .gnu.linkonce.t.*);

42
43
        /* C++ Support */

44
        KEEP(*(.init))

45
        KEEP(*(.fini))

46
47
        /* .ctors */

48
        *crtbegin.o(.ctors)

49
        *crtbegin?.o(.ctors)

50
        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)

51
        *(SORT(.ctors.*))

52
        *(.ctors)

53
54
        /* .dtors */

55
        *crtbegin.o(.dtors)

56
        *crtbegin?.o(.dtors)

57
        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)

58
        *(SORT(.dtors.*))

59
        *(.dtors)

60
61
        *(.rodata .rodata.*)

62
        *(.gnu.linkonce.r*)

63
        

64
        *(vtable)        

65
        . = ALIGN(4);        

66
    } > FLASH_1_cached AT > FLASH_1_uncached

67
68
    .eh_frame_hdr : ALIGN (4)

69
    {

70
      KEEP (*(.eh_frame_hdr))

71
    } > FLASH_1_cached AT > FLASH_1_uncached

72
  

73
    .eh_frame : ALIGN (4)

74
    {

75
      KEEP (*(.eh_frame))

76
    } > FLASH_1_cached AT > FLASH_1_uncached

77
78
    /* Exception handling, exidx needs a dedicated section */

79
    .ARM.extab : ALIGN(4)

80
    {

81
        *(.ARM.extab* .gnu.linkonce.armextab.*)

82
    } > FLASH_1_cached AT > FLASH_1_uncached

83
84
    . = ALIGN(4);

85
    __exidx_start = .;

86
    .ARM.exidx : ALIGN(4)

87
    {

88
        *(.ARM.exidx* .gnu.linkonce.armexidx.*)

89
    } > FLASH_1_cached AT > FLASH_1_uncached

90
    __exidx_end = .;

91
    . = ALIGN(4);

92
    

93
    /* DSRAM layout (Lowest to highest)*/

94
    Stack (NOLOAD) : 

95
    {

96
        __stack_start = .;

97
        . = . + stack_size;

98
        __stack_end = .;

99
        __initial_sp = .;

100
    } > SRAM_combined

101
102
    /* functions with __attribute__((section(".ram_code"))) */

103
    .ram_code :

104
    {

105
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

106
        __ram_code_start = .;

107
        *(.ram_code)

108
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

109
        __ram_code_end = .;

110
    } > SRAM_combined AT > FLASH_1_uncached

111
    __ram_code_load = LOADADDR (.ram_code);

112
    __ram_code_size = __ram_code_end - __ram_code_start;

113
114
    /* Standard DATA and user defined DATA/BSS/CONST sections */

115
    .data :

116
    {

117
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

118
        __data_start = .;

119
        * (.data);

120
        * (.data*);

121
        *(*.data);

122
        *(.gnu.linkonce.d*)

123
      

124
        . = ALIGN(4);

125
        /* preinit data */

126
        PROVIDE_HIDDEN (__preinit_array_start = .);

127
        KEEP(*(.preinit_array))

128
        PROVIDE_HIDDEN (__preinit_array_end = .);

129
130
        . = ALIGN(4);

131
        /* init data */

132
        PROVIDE_HIDDEN (__init_array_start = .);

133
        KEEP(*(SORT(.init_array.*)))

134
        KEEP(*(.init_array))

135
        PROVIDE_HIDDEN (__init_array_end = .);

136
137
        . = ALIGN(4);

138
        /* finit data */

139
        PROVIDE_HIDDEN (__fini_array_start = .);

140
        KEEP(*(SORT(.fini_array.*)))

141
        KEEP(*(.fini_array))

142
        PROVIDE_HIDDEN (__fini_array_end = .);

143
144
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

145
        __data_end = .;

146
    } > SRAM_combined AT > FLASH_1_uncached

147
    __data_load = LOADADDR (.data);

148
    __data_size = __data_end - __data_start;

149
        

150
    __text_size = (__exidx_end - sText) + __data_size + __ram_code_size;

151
    eText = sText + __text_size;

152
153
    /* BSS section */

154
    .bss (NOLOAD) : 

155
    {

156
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

157
        __bss_start = .;

158
        * (.bss);

159
        * (.bss*);

160
        * (COMMON);

161
        *(.gnu.linkonce.b*)

162
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

163
        __bss_end = .;

164
    } > SRAM_combined

165
    __bss_size = __bss_end - __bss_start;

166
167
    /* Shift location counter, so that ETH_RAM and USB_RAM are located above DSRAM_1_system */    

168
    __shift_loc =  (__bss_end >= ORIGIN(DSRAM_1_system)) ? 0 : (ORIGIN(DSRAM_1_system) - __bss_end);

169
170
    USB_RAM  (__bss_end + __shift_loc) (NOLOAD) :

171
    {

172
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

173
        USB_RAM_start = .;

174
        *(USB_RAM)

175
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

176
        USB_RAM_end = .;

177
    } > SRAM_combined

178
    USB_RAM_size = USB_RAM_end - USB_RAM_start;

179
180
    ETH_RAM (USB_RAM_end) (NOLOAD) :

181
    {

182
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

183
        ETH_RAM_start = .;

184
        *(ETH_RAM)

185
        . = ALIGN(4); /* section size must be multiply of 4. See startup.S file */

186
        ETH_RAM_end = .;

187
        . = ALIGN(8);

188
        Heap_Bank1_Start = .;

189
    } > SRAM_combined

190
    ETH_RAM_size = ETH_RAM_end - ETH_RAM_start;

191
192
    /* .no_init section contains chipid, SystemCoreClock and trimming data. See system.c file*/

193
    .no_init ORIGIN(SRAM_combined) + LENGTH(SRAM_combined) - no_init_size (NOLOAD) : 

194
    {

195
        Heap_Bank1_End = .;

196
        * (.no_init);

197
    } > SRAM_combined

198
199
    /* Heap - Bank1*/

200
    Heap_Bank1_Size  = Heap_Bank1_End - Heap_Bank1_Start;

201
202
    ASSERT(Heap_Bank1_Start <= Heap_Bank1_End, "region SRAM_combined overflowed no_init section")

203
204
    /DISCARD/ :

205
    {

206
        *(.comment)

207
    }

208
209
    .stab       0 (NOLOAD) : { *(.stab) }

210
    .stabstr    0 (NOLOAD) : { *(.stabstr) }

211
212
    /* DWARF 1 */

213
    .debug              0 : { *(.debug) }

214
    .line               0 : { *(.line) }

215
216
    /* GNU DWARF 1 extensions */

217
    .debug_srcinfo      0 : { *(.debug_srcinfo) }

218
    .debug_sfnames      0 : { *(.debug_sfnames) }

219
220
    /* DWARF 1.1 and DWARF 2 */

221
    .debug_aranges      0 : { *(.debug_aranges) }

222
    .debug_pubnames     0 : { *(.debug_pubnames) }

223
    .debug_pubtypes     0 : { *(.debug_pubtypes) }

224
225
    /* DWARF 2 */

226
    .debug_info         0 : { *(.debug_info .gnu.linkonce.wi.*) }

227
    .debug_abbrev       0 : { *(.debug_abbrev) }

228
    .debug_line         0 : { *(.debug_line) }

229
    .debug_frame        0 : { *(.debug_frame) }

230
    .debug_str          0 : { *(.debug_str) }

231
    .debug_loc          0 : { *(.debug_loc) }

232
    .debug_macinfo      0 : { *(.debug_macinfo) }

233
234
    /* DWARF 2.1 */

235
    .debug_ranges       0 : { *(.debug_ranges) }

236
237
    /* SGI/MIPS DWARF 2 extensions */

238
    .debug_weaknames    0 : { *(.debug_weaknames) }

239
    .debug_funcnames    0 : { *(.debug_funcnames) }

240
    .debug_typenames    0 : { *(.debug_typenames) }

241
    .debug_varnames     0 : { *(.debug_varnames) }

242
243
    /* Build attributes */

244
    .build_attributes   0 : { *(.ARM.attributes) }

245
}


  


  




  

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