IP Cache entry does not have the required number of cached files

[Zitty Z. (Firma: ZATT) (zitierer)]

Hallo guten Tag,

ich möchte eine Design synthetisieren.
Es kommt jedoch eine Warnung.
Weiß jemand was diese bedeutet:

[IP_Flow 19-5242] IP Cache entry (cache-ID 888fc04b930f26e1) does not have the required number of cached files and is not valid. Please delete this entry using the TCL command: 
'config_ip_cache -remove [get_ips xaui_0]'

Wenn man das ausführt in der tcl console erscheint :

config_ip_cache -remove [get_ips xaui_0]
WARNING: [Coretcl 2-1487] No matching IP cache entry found
0

------------------------------------------
Außerdem erscheint beim Schritt IMPLEMENTATION:

[Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["<habeichentfernt>/test.srcs/constrs_1/new/myconstraints.xdc":26]

wobei

set_property PACKAGE_PIN E13            [ get_ports x_mgt216_clk_n_i ]

wo ist da das Problem?

Beim I/O planning sieht man folgendes:

E13  0  false  null  null  null  null  I/O Bank 216  MGT  null  Gigabit  null  null  null  null  null  MGTREFCLK1N  null  null  62.882  63.514  IPAD_X1Y47  MGTREFCLK1N_216

der xaui core hat die shareable Logik im core.
 Muss man auch im Re-custimize IP editor auswählen.
lt datenblatt ist dort IBUFDS_GTE2 enthalten:
dort ist refclk_p und refclk_n angeschlossen.

Allerdings kommt hier beim IMPLEMENTATION Schritt eine Fehlermeldung:

DRC
Netlist
Instance
Required Pin
IBUFDS_GTE2

[DRC REQP-1619] IBUFDS_GTE2_driven_by_IBUF: IBUFDS_GTE2 xaui_core/U0/xaui_support_clocking_i/refclk_ibufds pins I and IB should be driven by IBUFs.
[Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run.

I and IB should be driven by IBUFs: soll man IBUFs einbauen?

Hab das wahrscheinlich falsch verbunden.

entity xaui_0_support_clocking is
    port (
      refclk_p             : in  std_logic;
      refclk_n             : in  std_logic;
      refclk               : out std_logic
      );

refclk_p_ibuf_inst : IBUF
  generic map (
    IBUF_LOW_PWR => FALSE,              -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    IOSTANDARD   => "DEFAULT")         -- Specify the input I/O standard
  port map (
    O            => refclk_p_ibuf,     -- Buffer output
    I            => refclk_p           -- Buffer input (connect directly to top-level port)
  );
  refclk_n_ibuf_inst : IBUF
  generic map (
    IBUF_LOW_PWR => FALSE,              -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
    IOSTANDARD   => "DEFAULT")         -- Specify the input I/O standard
  port map (
    O            => refclk_n_ibuf,     -- Buffer output
    I            => refclk_n           -- Buffer input (connect directly to top-level port)
  );

  -- Differential Clock Module
    refclk_ibufds : IBUFDS_GTE2
    port map (
      I          => refclk_p_ibuf,
      IB         => refclk_n_ibuf,
      O          => refclk,
      CEB        => '0',
      ODIV2      => open );

Nutze Vivado 2019.1

[druck-spezialist (Gast)]

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If 
this sub optimal condition is acceptable for this design, you may use 
the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this 
message to a WARNING. However, the use of this override is highly 
discouraged. These examples can be used directly in the .xdc file to 
override this clock rule.
  < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets 
a7_mgt216_clk_p_i_IBUF] >

  a7_mgt216_clk_p_i_IBUF_inst (IBUF.O) is locked to IPAD_X1Y44
   a7_mgt216_clk_p_i_IBUF_BUFG_inst (BUFG.I) is provisionally placed by 
clockplacer on BUFGCTRL_X0Y31

  The above error could possibly be related to other connected 
instances. Following is a list of
  all the related clock rules and their respective instances.

  Clock Rule: rule_bufds_gtp_common_intelligent_pin
  Status: PASS
  Rule Description: A BUFDS driving a GTPCommon must both be placed in 
the same or adjacent clock region
  (top/bottom)
   xaui_core/U0/xaui_support_clocking_i/refclk_ibufds (IBUFDS_GTE2.O) is 
locked to IBUFDS_GTE2_X0Y2
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gtpe2_common_0_i 
(GTPE2_COMMON.GTREFCLK0) is provisionally placed by clockplacer on 
GTPE2_COMMON_X0Y1

  Clock Rule: rule_gtpcommon_gtpchannel
  Status: PASS
  Rule Description: A GTPCommon driving a GTPChannel must both be in the 
same clock region
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gtpe2_common_0_i 
(GTPE2_COMMON.PLL0OUTCLK) is provisionally placed by clockplacer on 
GTPE2_COMMON_X0Y1
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gt1_xaui_0_gt_wrapper_i/gtpe2_i 
(GTPE2_CHANNEL.PLL0CLK) is locked to GTPE2_CHANNEL_X0Y5
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gt2_xaui_0_gt_wrapper_i/gtpe2_i 
(GTPE2_CHANNEL.PLL0CLK) is locked to GTPE2_CHANNEL_X0Y6
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gt3_xaui_0_gt_wrapper_i/gtpe2_i 
(GTPE2_CHANNEL.PLL0CLK) is locked to GTPE2_CHANNEL_X0Y7
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gt0_xaui_0_gt_wrapper_i/gtpe2_i 
(GTPE2_CHANNEL.PLL0CLK) is locked to GTPE2_CHANNEL_X0Y4

  Clock Rule: rule_gt_bufg
  Status: PASS
  Rule Description: A GT driving a BUFG must be placed on the same half 
side (top/bottom) of the device
   xaui_core/U0/xaui_block_i/gt_wrapper_i/gt0_xaui_0_gt_wrapper_i/gtpe2_i 
(GTPE2_CHANNEL.TXOUTCLK) is locked to GTPE2_CHANNEL_X0Y4
   and xaui_core/U0/xaui_block_i/xaui_cl_clocking_i/clk156_bufg_i 
(BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y30