Kann Mir bitte jemand sagen was an den folgenden code falsch ist. Die Ausgangssignale sind anscheinend undefiniert wobei ich gar nix gefunden hab.
1 | library ieee; |
2 | use ieee.std_logic_1164.all; |
3 | |
4 | entity ErrGen_PNGEN7 is |
5 | port( |
6 | clock : in std_logic; |
7 | reset : in std_logic; |
8 | ErrEn : in std_logic; |
9 | PNTrig : out std_logic; |
10 | PNOut : out std_logic; |
11 | ErrSeqOut : out std_logic |
12 | );
|
13 | end entity ErrGen_PNGEN7; |
14 | |
15 | architecture ErrGen_PNGEN7_arch of ErrGen_PNGEN7 is |
16 | |
17 | component PNGEN7 |
18 | port( clock : in std_logic; |
19 | reset : in std_logic; |
20 | pntrig : out std_logic; |
21 | pnser : out std_logic ); |
22 | end component; |
23 | |
24 | component ErrGen |
25 | generic(Width : natural := 7); |
26 | port( clock : in std_logic; |
27 | reset : in std_logic; |
28 | ErrEn : in std_logic; |
29 | TxDIn : in std_logic; |
30 | ErrSerOut : out std_logic ); |
31 | end component; |
32 | |
33 | signal s_pnser : std_logic; |
34 | |
35 | begin
|
36 | seq_gen: PNGEN7 port map( clock => clock, |
37 | reset => reset, |
38 | pntrig => PNTrig, |
39 | pnser => s_pnser ); |
40 | |
41 | ErrFade: ErrGen port map( clock => clock, |
42 | reset => reset, |
43 | ErrEn => ErrEn, |
44 | TxDIn => s_pnser, |
45 | ErrSerOut => ErrSeqOut ); |
46 | |
47 | PNOut <= s_pnser; |
48 | |
49 | end architecture; |