1 | #define __TIM4_PERIOD 0x003E8 // 48
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2 | #define __TIM4_PSC 0x1C1F // 49
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3 | #define __TIM4_ARR 0x270F // 50
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4 | #define __TIM4_CR1 0x0004 // 51
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5 | #define __TIM4_CR2 0x0000 // 52
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6 | #define __TIM4_SMCR 0x0000 // 53
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7 | #define __TIM4_CCMR1 0x0000 // 54
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8 | #define __TIM4_CCMR2 0x6060 // 55
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9 | #define __TIM4_CCER 0x1100 // 56
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10 | #define __TIM4_CCR1 0x0000 // 57
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11 | #define __TIM4_CCR2 0x0000 // 58
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12 | #define __TIM4_CCR3 0x1388 // 59
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13 | #define __TIM4_CCR4 0x09C4 // 60
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14 | #define __TIM4_DIER 0x0018 // 61
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15 | #define __CLOCK_SETUP 1
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16 | #define __RCC_CR_VAL 0x01010082
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17 | #define __RCC_CFGR_VAL 0x001D8402
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18 | #define __HSE
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19 |
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20 |
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21 |
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22 |
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23 | void init(void)
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24 | {
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25 |
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26 | RCC->CFGR = __RCC_CFGR_VAL; // set clock configuration register
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27 | RCC->CR = __RCC_CR_VAL; // set clock control register
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28 |
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29 | if (__RCC_CR_VAL & RCC_CR_HSION) { // if HSI enabled
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30 | while ((RCC->CR & RCC_CR_HSIRDY) == 0); //Wait HSIRDY=1 (HSI is ready)
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31 | }
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32 |
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33 | if (__RCC_CR_VAL & RCC_CR_HSEON) { // if HSE enabled
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34 | while ((RCC->CR & RCC_CR_HSERDY) == 0); //Wait HSERDY=1 (HSE is ready)
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35 | }
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36 |
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37 | if (__RCC_CR_VAL & RCC_CR_PLLON) { // if PLL enabled
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38 | while ((RCC->CR & RCC_CR_PLLRDY) == 0); //Wait PLLRDY=1 (PLL is ready)
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39 | }
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40 |
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41 | /* Wait till SYSCLK is stabilized (depending on selected clock) */
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42 | while ((RCC->CFGR & RCC_CFGR_SWS) != ((__RCC_CFGR_VAL<<2) & RCC_CFGR_SWS));
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43 |
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44 |
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45 |
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46 |
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47 | RCC->APB1ENR |= RCC_APB1ENR_TIM4EN; // enable clock for TIM4
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48 |
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49 |
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50 | TIM4->CR1 = 0; // reset command register 1
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51 | TIM4->CR2 = 0; // reset command register 2
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52 | // detailed settings used
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53 | TIM4->PSC = __TIM4_PSC; // set prescaler
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54 | TIM4->ARR = __TIM4_ARR; // set auto-reload
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55 |
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56 | TIM4->CCR1 = __TIM4_CCR1; //
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57 | TIM4->CCR2 = __TIM4_CCR2; //
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58 | TIM4->CCR3 = __TIM4_CCR3; //
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59 | TIM4->CCR4 = __TIM4_CCR4; //
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60 | TIM4->CCMR1 = __TIM4_CCMR1; //
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61 | TIM4->CCMR2 = __TIM4_CCMR2; //
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62 | TIM4->CCER = __TIM4_CCER; // set capture/compare enable register
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63 | TIM4->SMCR = __TIM4_SMCR; // set slave mode control register
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64 |
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65 | TIM4->CR1 = __TIM4_CR1; // set command register 1
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66 | TIM4->CR2 = __TIM4_CR2;
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67 |
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68 | }
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