1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | entity RS232 is
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6 | Generic ( Quarz_Taktfrequenz : integer := 50000000; -- Hertz
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7 | Baudrate : integer := 9600 -- Bits/Sec
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8 | );
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9 | Port ( RXD : in STD_LOGIC;
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10 | TXD : out STD_LOGIC;
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11 | CLK : in STD_LOGIC;
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12 | LED : out STD_LOGIC_VECTOR (7 downto 0)
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13 |
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14 | );
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15 | end RS232;
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16 |
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17 | architecture Behavioral of RS232 is
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18 |
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19 | signal txstart : std_logic;
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20 | signal txsr : std_logic_vector (9 downto 0) := "1111111111"; -- Startbit, 8 Datenbits, Stopbit
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21 | signal txbitcnt : integer range 0 to 10 := 10;
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22 | signal txcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1;
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23 |
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24 | signal rxd_sr : std_logic_vector (3 downto 0) := "1111"; -- Flankenerkennung und Eintakten
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25 | signal rxsr : std_logic_vector (7 downto 0) := "00000000"; -- 8 Datenbits
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26 | signal rxbitcnt : integer range 0 to 9 := 9;
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27 | signal rxcnt : integer range 0 to (Quarz_Taktfrequenz/Baudrate)-1;
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28 |
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29 | ---------------------------------------------------------------------------
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30 | signal counter: integer range 0 to 50000000 :=0;
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31 | --
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32 | --
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33 | signal RX_Data : STD_LOGIC_VECTOR (7 downto 0);
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34 | signal RX_Busy : STD_LOGIC;
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35 | signal TX_Data : STD_LOGIC_VECTOR (7 downto 0):= "10101010";
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36 | signal TX_Start : STD_LOGIC;
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37 | signal TX_Busy : STD_LOGIC;
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38 |
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39 | ---------------------------------------------------------------------------
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40 |
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41 | begin
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42 |
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43 | process (CLK)begin
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44 | If rising_edge(CLK) then
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45 | If counter < Quarz_Taktfrequenz/2 then
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46 | TX_Start <= '1';
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47 | -- txstart <= '0';
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48 |
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49 | elsif counter = Quarz_Taktfrequenz then
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50 | counter <= 0;
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51 | else
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52 | --LED(1) <= '1';
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53 | TX_Start <= '0';
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54 | -- txstart <= '1';
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55 | end if;
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56 | end if;
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57 | end process;
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58 |
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59 | -- Senden
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60 | process begin
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61 | wait until rising_edge(CLK);
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62 | txstart <= TX_Start;
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63 | if (TX_Start='1' and txstart='0') then -- steigende Flanke, los gehts
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64 |
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65 | txcnt <= 0; -- Zähler initialisieren
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66 | txbitcnt <= 0;
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67 | txsr <= '1' & TX_Data & '0'; -- Stopbit, 8 Datenbits, Startbit, rechts gehts los
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68 | --LED(0) <= '1';
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69 | else
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70 | if(txcnt<(Quarz_Taktfrequenz/Baudrate)-1) then
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71 | txcnt <= txcnt+1;
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72 | else -- nächstes Bit ausgeben
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73 | if (txbitcnt<10) then
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74 |
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75 | txcnt <= 0;
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76 | txbitcnt <= txbitcnt+1;
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77 | txsr <= '1' & txsr(txsr'left downto 1);
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78 | end if;
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79 | end if;
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80 | end if;
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81 | end process;
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82 |
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83 | TXD <= txsr(0); -- LSB first
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84 | TX_Busy <= '1' when (TX_Start='1' or txbitcnt<10) else '0';
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85 | --LED(2) <= '1';
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86 | -- Empfangen
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87 | process begin
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88 | wait until rising_edge(CLK);
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89 | rxd_sr <= rxd_sr(rxd_sr'left-1 downto 0) & RXD;
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90 | if (rxbitcnt<9) then -- Empfang läuft
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91 | if(rxcnt<(Quarz_Taktfrequenz/Baudrate)-1) then
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92 | rxcnt <= rxcnt+1;
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93 | else
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94 | rxcnt <= 0;
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95 | rxbitcnt <= rxbitcnt+1;
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96 | rxsr <= rxd_sr(rxd_sr'left-1) & rxsr(rxsr'left downto 1); -- rechts schieben, weil LSB first
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97 | end if;
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98 | else -- warten auf Startbit
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99 | if (rxd_sr(3 downto 2) = "10") then -- fallende Flanke Startbit
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100 | rxcnt <= ((Quarz_Taktfrequenz/Baudrate)-1)/2; -- erst mal nur halbe Bitzeit abwarten
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101 | rxbitcnt <= 0;
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102 | end if;
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103 | end if;
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104 | end process;
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105 | RX_Data <= rxsr;
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106 | LED <= RX_Data;
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107 | RX_Busy <= '1' when (rxbitcnt<9) else '0';
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108 |
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109 | end Behavioral;
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