1 | Started : "Synthesize - XST".
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2 | Running xst...
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3 | Command Line: xst -intstyle ise -ifn "D:/Christian/FPGA/Test_S6T/top.xst" -ofn "D:/Christian/FPGA/Test_S6T/top.syr"
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4 | Reading design: top.prj
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5 |
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6 | =========================================================================
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7 | * HDL Parsing *
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8 | =========================================================================
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9 | Parsing VHDL file "D:\Christian\FPGA\Test_S6T\Test.vhd" into library work
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10 | Parsing entity <top>.
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11 | Parsing architecture <Behavioral> of entity <top>.
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12 |
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13 | =========================================================================
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14 | * HDL Elaboration *
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15 | =========================================================================
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16 |
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17 | Elaborating entity <top> (architecture <Behavioral>) with generics from library <work>.
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18 |
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19 | =========================================================================
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20 | * HDL Synthesis *
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21 | =========================================================================
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22 |
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23 | Synthesizing Unit <top>.
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24 | Related source file is "d:/christian/fpga/test_s6t/test.vhd".
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25 | WIDTH = 8
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26 | Found 3-bit register for signal <bits>.
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27 | Found 8-bit register for signal <PAR_DAT>.
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28 | Found 8-bit register for signal <serdat>.
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29 | Found 3-bit adder for signal <bits[2]_GND_3_o_add_1_OUT> created at line 21.
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30 | Found 3-bit comparator greater for signal <bits[2]_PWR_3_o_LessThan_1_o> created at line 20
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31 | Summary:
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32 | inferred 1 Adder/Subtractor(s).
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33 | inferred 19 D-type flip-flop(s).
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34 | inferred 1 Comparator(s).
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35 | Unit <top> synthesized.
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36 |
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37 | =========================================================================
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38 | HDL Synthesis Report
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39 |
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40 | Macro Statistics
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41 | # Adders/Subtractors : 1
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42 | 3-bit adder : 1
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43 | # Registers : 3
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44 | 3-bit register : 1
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45 | 8-bit register : 2
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46 | # Comparators : 1
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47 | 3-bit comparator greater : 1
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48 |
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49 | =========================================================================
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50 |
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51 | =========================================================================
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52 | * Advanced HDL Synthesis *
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53 | =========================================================================
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54 |
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55 |
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56 | Synthesizing (advanced) Unit <top>.
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57 | The following registers are absorbed into counter <bits>: 1 register on signal <bits>.
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58 | Unit <top> synthesized (advanced).
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59 |
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60 | =========================================================================
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61 | Advanced HDL Synthesis Report
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62 |
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63 | Macro Statistics
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64 | # Counters : 1
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65 | 3-bit up counter : 1
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66 | # Registers : 16
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67 | Flip-Flops : 16
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68 | # Comparators : 1
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69 | 3-bit comparator greater : 1
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70 |
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71 | =========================================================================
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72 |
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73 | =========================================================================
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74 | * Low Level Synthesis *
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75 | =========================================================================
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76 |
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77 | Optimizing unit <top> ...
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78 |
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79 | Mapping all equations...
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80 | Building and optimizing final netlist ...
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81 | Found area constraint ratio of 100 (+ 5) on block top, actual ratio is 0.
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82 |
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83 | Final Macro Processing ...
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84 |
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85 | =========================================================================
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86 | Final Register Report
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87 |
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88 | Macro Statistics
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89 | # Registers : 19
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90 | Flip-Flops : 19
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91 |
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92 | =========================================================================
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93 |
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94 | =========================================================================
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95 | * Partition Report *
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96 | =========================================================================
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97 |
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98 | Partition Implementation Status
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99 | -------------------------------
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100 |
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101 | No Partitions were found in this design.
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102 |
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103 | -------------------------------
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104 |
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105 | =========================================================================
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106 | * Design Summary *
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107 | =========================================================================
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108 |
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109 | Clock Information:
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110 | ------------------
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111 | -----------------------------------+------------------------+-------+
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112 | Clock Signal | Clock buffer(FF name) | Load |
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113 | -----------------------------------+------------------------+-------+
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114 | CLK | BUFGP | 19 |
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115 | -----------------------------------+------------------------+-------+
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116 |
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117 | Asynchronous Control Signals Information:
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118 | ----------------------------------------
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119 | No asynchronous control signals found in this design
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120 |
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121 | Timing Summary:
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122 | ---------------
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123 | Speed Grade: -3
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124 |
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125 | Minimum period: 2.216ns (Maximum Frequency: 451.233MHz)
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126 | Minimum input arrival time before clock: 1.903ns
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127 | Maximum output required time after clock: 3.634ns
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128 | Maximum combinational path delay: No path found
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129 |
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130 | =========================================================================
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131 |
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132 | Process "Synthesize - XST" completed successfully
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