1 | #include <avr/io.h>
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2 | #include <avr/interrupt.h>
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3 |
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4 | // ----- Pin maps (see scematics) -----
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5 | #define SATELIT_CLK PA1
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6 |
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7 | // ----- Makros -----
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8 | #define FASTER_CLK_ON PORTA |= (1<<SATELIT_CLK) // high
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9 | #define FASTER_CLK_OFF PORTA &= ~(1<<SATELIT_CLK) // low
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10 |
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11 | // ----- Timer -----
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12 | // number of clockcycles of equal length *2 you want to insert between to clock cycles on ICP1 input capture pin
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13 | #define CLK_multiplier_times_2 8
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14 |
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15 | void Toggle_Clock(void)
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16 | {
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17 | // static variables for faster access compared to global
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18 | static unsigned int full_interval_length = 0;
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19 | static char Pin_level_state = 0;
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20 | static char Clock_state = 0;
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21 | static unsigned int timing_vector[CLK_multiplier_times_2];
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22 |
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23 | // Toggle faster clock
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24 | if (Pin_level_state){
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25 | FASTER_CLK_OFF;
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26 | Pin_level_state = 0;
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27 | }
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28 | else{
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29 | FASTER_CLK_ON;
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30 | Pin_level_state = 1;
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31 | }
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32 |
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33 | if (Clock_state == 0){
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34 | // new cycles starts
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35 | // prepare timing vector
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36 | // read measured interval length between two slower clock pulses
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37 | full_interval_length = ICR1;
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38 |
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39 | char rest = full_interval_length % 8;// rest of division by 8
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40 |
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41 | timing_vector[0] = (1*full_interval_length)/CLK_multiplier_times_2;
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42 | timing_vector[1] = (2*full_interval_length)/CLK_multiplier_times_2;
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43 | timing_vector[2] = (3*full_interval_length)/CLK_multiplier_times_2;
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44 | timing_vector[3] = (4*full_interval_length)/CLK_multiplier_times_2;
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45 | timing_vector[4] = (5*full_interval_length)/CLK_multiplier_times_2;
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46 | timing_vector[5] = (6*full_interval_length)/CLK_multiplier_times_2;
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47 | timing_vector[6] = (7*full_interval_length)/CLK_multiplier_times_2;
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48 | timing_vector[7] = 0xFFFE;// Dummy, timer should never reach this value. external slower clock ISR should appear before this happens.
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49 |
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50 | // divide rest of division "equaly" over the timers
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51 | if (rest == 1){
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52 | timing_vector[3]++;
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53 | }
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54 | else if (rest == 2){
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55 | timing_vector[2]++;
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56 | timing_vector[4]++;
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57 | }
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58 | else if (rest == 3){
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59 | timing_vector[1]++;
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60 | timing_vector[3]++;
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61 | timing_vector[5]++;
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62 | }
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63 | else if (rest == 4){
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64 | timing_vector[0]++;
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65 | timing_vector[2]++;
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66 | timing_vector[4]++;
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67 | timing_vector[6]++;
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68 | }
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69 | else if (rest == 5){
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70 | timing_vector[0]++;
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71 | timing_vector[1]++;
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72 | timing_vector[3]++;
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73 | timing_vector[5]++;
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74 | timing_vector[6]++;
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75 | }
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76 | else if (rest == 6){
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77 | timing_vector[0]++;
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78 | timing_vector[1]++;
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79 | timing_vector[2]++;
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80 | timing_vector[4]++;
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81 | timing_vector[5]++;
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82 | timing_vector[6]++;
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83 | }
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84 | else if (rest == 7){
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85 | timing_vector[0]++;
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86 | timing_vector[1]++;
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87 | timing_vector[2]++;
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88 | timing_vector[3]++;
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89 | timing_vector[4]++;
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90 | timing_vector[5]++;
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91 | timing_vector[6]++;
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92 | }
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93 | }
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94 |
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95 | OCR1A = timing_vector[Clock_state];// set time for next satellite clk event
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96 |
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97 | Clock_state++; // increment faster clk cycle counter
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98 | if (Clock_state == 8){
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99 | Clock_state = 0; // reset cycle
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100 | }
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101 |
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102 | // it is necessary to reach end of this before "timing_vector[Clock_state]" MCU cycles
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103 | }
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104 |
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105 | ISR(TIMER1_CAPT_vect)
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106 | {
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107 | // ICR1 is set to TCNT1 by hardware.
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108 | TCNT1 = 0; // reset current value of timer 1.
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109 | Toggle_Clock(); // Toggle faster clock
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110 | }
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111 |
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112 | ISR(TIMER1_COMPA_vect)
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113 | {
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114 |
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115 | OCR1A = 0xFFFE;// Dummy 16-bit access that "should" take as long as TCNT1 = 0;.Timer should never reach this value.
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116 | Toggle_Clock(); // Toggle faster clock
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117 | }
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118 |
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119 | int main(void)
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120 | {
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121 | // ----- Hardware -----
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122 | // GPIOs
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123 | FASTER_CLK_OFF;
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124 | DDRA |= (1 << SATELIT_CLK);
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125 |
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126 | // ----- Timer 1 -----
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127 | TCCR1B |= (1<<ICES1); // Trigger positive edge
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128 |
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129 | //CS12 CS11 CS10 Description
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130 | //0 0 0 No clock source (Timer/Counter stopped).
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131 | //0 0 1 clkI/O/1 (No prescaling)
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132 | //0 1 0 clkI/O/8 (From prescaler)
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133 | //0 1 1 clkI/O/64 (From prescaler)
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134 | //1 0 0 clkI/O/256 (From prescaler)
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135 | //1 0 1 clkI/O/1024 (From prescaler)
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136 | //1 1 0 External clock source on T1 pin. Clock on falling edge.
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137 | //1 1 1 External clock source on T1 pin. Clock on rising edge.
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138 |
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139 | // prescaler = 1
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140 | //TCCR1B |= (1<<CS12);
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141 | TCCR1B &= ~(1 <<CS12);
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142 | //TCCR1B |= (1<<CS11);
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143 | TCCR1B &= ~(1 <<CS11);
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144 | TCCR1B |= (1<<CS10);
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145 | //TCCR1B &= ~(1 <<CS10);
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146 |
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147 | OCR1A = 0xFFFE; // Dummy, should never be reached - if slower clock is present
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148 |
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149 | // integrate overflow ISR depending on what you wnat to do when no slow clock is present
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150 | //TIMSK &= ~(1 <<TOIE1); // overflow ISR
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151 | TIMSK |= (1 <<ICIE1 ); // Input Capture Interrupt Enable
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152 | TIMSK |= (1 <<OCIE1A); // compare A match enable
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153 | while(1){}
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154 | }
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