1 | /* Initialisierung vom FSMC Bus */
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2 |
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3 | FSMC_NORSRAMInitTypeDef FSMC_NORSRAMInitStructure;
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4 | FSMC_NORSRAMTimingInitTypeDef p;
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5 |
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6 | RCC->AHBENR |= RCC_AHBPeriph_FSMC;
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7 | RCC->APB2ENR |= (RCC_APB2Periph_GPIOD | RCC_APB2Periph_GPIOG | RCC_APB2Periph_GPIOE | RCC_APB2Periph_GPIOF) ;
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8 |
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9 | GPIO_Init(GPIOD, GPIO_Mode_AF_PP, (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 | GPIO_Pin_15));
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10 |
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11 | GPIO_Init(GPIOD, GPIO_Mode_AF_PP, (GPIO_Pin_7 | GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 | GPIO_Pin_14 |
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12 | GPIO_Pin_15));
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13 |
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14 | GPIO_Init(GPIOF, GPIO_Mode_AF_PP, ( GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_12 | GPIO_Pin_13 |
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15 | GPIO_Pin_14 | GPIO_Pin_15));
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16 |
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17 | GPIO_Init(GPIOG, GPIO_Mode_AF_PP, (GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5));
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18 |
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19 |
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20 | GPIO_Init(GPIOD, GPIO_Mode_AF_PP, (GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13));
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21 |
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22 | GPIO_Init(GPIOD, GPIO_Mode_AF_PP, (GPIO_Pin_4 |GPIO_Pin_5)); //NWE, NOE
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23 | GPIO_Init(GPIOG, GPIO_Mode_AF_PP, (GPIO_Pin_9 | GPIO_Pin_10)); //NCS0 NCS1
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24 | GPIO_Init(GPIOE, GPIO_Mode_AF_PP, (GPIO_Pin_0 | GPIO_Pin_1));
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25 |
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26 |
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27 | p.FSMC_AddressSetupTime = 1;
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28 | p.FSMC_AddressHoldTime = 1;
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29 | p.FSMC_DataSetupTime = 1;
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30 | p.FSMC_BusTurnAroundDuration = 0;
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31 | p.FSMC_CLKDivision = 16; //72MHz / 16
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32 | p.FSMC_DataLatency = 0;
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33 | p.FSMC_AccessMode = FSMC_AccessMode_A;
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34 |
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35 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
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36 | FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
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37 | FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
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38 | FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
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39 | FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
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40 | FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
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41 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
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42 | FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
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43 | FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
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44 | FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
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45 | FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
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46 | FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
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47 | FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
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48 | FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
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49 | FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
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50 |
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51 | FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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52 |
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53 | FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
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54 | FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure);
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55 |
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56 | /*!< Enable FSMC Bank1_SRAM Bank */
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57 | FSMC_Bank1->BTCR[FSMC_Bank1_NORSRAM3] |= BCR_MBKEN_Set;
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58 | FSMC_Bank1->BTCR[FSMC_Bank1_NORSRAM2] |= BCR_MBKEN_Set;
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