1 | ----------------------------------------------------------------------------------
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2 | -- Company:
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3 | -- Engineer:
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4 | --
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5 | -- Create Date: 10:01:07 02/27/2012
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6 | -- Design Name:
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7 | -- Module Name: fsm - Behavioral
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8 | -- Project Name:
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9 | -- Target Devices:
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10 | -- Tool versions:
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11 | -- Description:
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12 | --
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13 | -- Dependencies:
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14 | --
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15 | -- Revision:
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16 | -- Revision 0.01 - File Created
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17 | -- Additional Comments:
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18 | --
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19 | ----------------------------------------------------------------------------------
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20 | library IEEE;
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21 | use IEEE.STD_LOGIC_1164.ALL;
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22 |
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23 | -- Uncomment the following library declaration if using
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24 | -- arithmetic functions with Signed or Unsigned values
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25 | use IEEE.NUMERIC_STD.ALL;
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26 |
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27 | -- Uncomment the following library declaration if instantiating
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28 | -- any Xilinx primitives in this code.
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29 | --library UNISIM;
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30 | --use UNISIM.VComponents.all;
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31 |
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32 | entity fsm is
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33 | Port ( clk : in STD_LOGIC;
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34 | res_n : in STD_LOGIC;
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35 | lcd_e : out STD_LOGIC;
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36 | lcd_rs : out STD_LOGIC;
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37 | lcd_rw : out STD_LOGIC;
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38 | lcd_db : inout STD_LOGIC_VECTOR (7 downto 0));
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39 | end fsm;
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40 |
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41 | architecture Behavioral of fsm is
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42 |
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43 | constant delay_40ms : integer := 4000000;
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44 | constant delay_37us : integer := 3700;
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45 | constant delay_1520us : integer := 152000;
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46 | constant tsu : integer := 0; -- RS, R/W setup time (min. 0ns)
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47 | constant twdsu : integer := 8; -- Write data setup time (min. 80ns)
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48 | constant tdh : integer := 30; -- Data hold time (min. 300ns)
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49 | constant th : integer := 1; -- RS, R/W hold time (min. 10ns)
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50 |
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51 | type state_type is (boot, function_set1, function_set2, disp_ctr, disp_clr, disp_entr, write_letter,idle);
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52 | signal current_state : state_type := boot;
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53 | signal cnt : integer range 0 to delay_40ms := 0;
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54 |
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55 | begin
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56 |
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57 | process(clk) is
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58 |
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59 | begin
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60 | if rising_edge(clk) then
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61 | case current_state is
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62 | when boot => if cnt < delay_40ms then
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63 | cnt <= cnt + 1;
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64 | current_state <= boot;
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65 | else
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66 | cnt <= 0;
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67 | current_state <= function_set1;
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68 | end if;
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69 |
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70 | when function_set1 => lcd_rs <= '0';
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71 | lcd_rw <= '0';
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72 | lcd_db <= "001110" & '-' & '-';
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73 |
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74 | if cnt < delay_37us then
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75 | cnt <= cnt + 1;
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76 | current_state <= function_set1;
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77 | else
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78 | cnt <= 0;
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79 | current_state <= function_set2;
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80 | end if;
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81 |
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82 | when function_set2 => lcd_rs <= '0';
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83 | lcd_rw <= '0';
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84 | lcd_db <= "001110" & '-' & '-';
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85 | if cnt < delay_37us then
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86 | cnt <= cnt + 1;
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87 | current_state <= function_set2;
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88 | else
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89 | cnt <= 0;
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90 | current_state <= disp_ctr;
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91 | end if;
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92 |
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93 | when disp_ctr => lcd_rs <= '0';
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94 | lcd_rw <= '0';
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95 | lcd_db <= "00001111";
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96 | if cnt < delay_37us then
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97 | cnt <= cnt + 1;
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98 | current_state <= disp_ctr;
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99 | else
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100 | cnt <= 0;
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101 | current_state <= disp_clr;
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102 | end if;
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103 |
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104 | when disp_clr => lcd_rs <= '0';
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105 | lcd_rw <= '0';
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106 | lcd_db <= "00000001";
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107 | if cnt < delay_1520us then
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108 | cnt <= cnt + 1;
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109 | current_state <= disp_clr;
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110 | else
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111 | cnt <= 0;
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112 | current_state <= disp_entr;
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113 | end if;
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114 | when disp_entr => lcd_rs <= '0';
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115 | lcd_rw <= '0';
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116 | lcd_db <= "00000110";
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117 | if cnt < delay_37us then
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118 | cnt <= cnt + 1;
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119 | current_state <= disp_entr;
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120 | else
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121 | cnt <= 0;
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122 | current_state <= write_letter;
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123 | end if;
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124 | when write_letter => if cnt < twdsu then
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125 | lcd_e <= '1';
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126 | lcd_rw <= '0';
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127 | lcd_rs <= '1';
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128 | lcd_db <= "01000001";
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129 | cnt <= cnt + 1;
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130 | elsif cnt = twdsu then
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131 | lcd_e <= '0';
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132 | cnt <= cnt + 1;
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133 | elsif cnt < twdsu + th then
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134 | cnt <= cnt + 1;
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135 | elsif cnt = twdsu + th then
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136 | lcd_rw <= '1';
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137 | cnt <= cnt + 1;
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138 | else
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139 | cnt <= 0;
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140 | current_state <= idle;
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141 | end if;
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142 |
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143 | when idle => lcd_e <= '1';
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144 | lcd_rw <= '1';
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145 | lcd_db <= "--------";
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146 |
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147 | current_state <= idle;
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148 | end case;
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149 | end if;
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150 | end process f;
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151 |
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152 | end Behavioral;
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