1 | void can_prepare(void) {
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2 | /* IRQ pin as input with pullup */
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3 | DDRB &= ~_BV(PB1);
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4 | PORTB |= _BV(PB1);
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5 |
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6 |
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7 | /* Reset */
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8 | can_command(CAN_RESET);
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9 | _delay_ms(100);
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10 |
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11 |
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12 | /* Tie BF pins */
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13 | can_write_register(BFPCTRL,
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14 | _BV(B1BFE) | _BV(B1BFM) | _BV(B0BFE) | _BV(B0BFM)
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15 | );
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16 |
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17 | /* Disable RTS pins */
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18 | can_write_register(TXRTSCTRL, 0);
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19 |
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20 |
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21 | /* Configure baud rate to 100kbps.
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22 | Given by the quartz oscillator used in the circuit:
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23 | Fosc = 8 MHz -> Tosc = 125 ns
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24 |
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25 | The nominal baud rate 'NBR' of 100 kbps is also the
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26 | nominal bit rate. This yields a nominal bit time of
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27 | Tbit = 1/NBR = 10 us
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28 |
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29 | The bit time is divided into time quants 'Tq' by the can
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30 | bus controller and the bit time is composed out of time
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31 | quants as
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32 | Tbit = Tsync + Tprop + Tpha1 + Tpha2
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33 | where
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34 | . Tsync is fixed to 1*Tq for synchronization to the bus,
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35 | . Tprop is the physical propagation delay on the bus,
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36 | . Tpha1 and Tpha2 divide the remaining bit time into
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37 | two phase segments. The bit is sampled between these
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38 | phase segments.
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39 |
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40 | The time quant must be choosen short enough to allow for
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41 | a sensible choice of the propagation sement Tprop and large
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42 | enough to be able to divide the total bit time at a ratio
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43 | of about 60..70% : 40..30%.
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44 |
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45 | The time quant is determined by a prescaler 'BRP'.
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46 | Tq = 2*(BRP+1) * Tosc
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47 | Choosing 'BRP' = 2 yields Tq = 1 us.
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48 |
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49 | The propagation delay is programmed by 'PRSEG' as
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50 | Tprop = (PRSEG+1) * Tq
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51 | and 'PRSEG' = 1 gives a propagation delay of 2 us, which
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52 | is enough for a tiny bus.
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53 |
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54 | After Tsync and Tprop, there are 6 time quants left.
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55 | Splitting the total bit time at a ratio of 70% : 30% makes
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56 | 7 time quants before and 3 after the sampling point. As
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57 | 3 time quants have already been used up by synchronization
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58 | and propagation, there are 4 time quants left for the first
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59 | phase segment and another 3 for the second one.
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60 | Tpha1 = (PHSEG1+1) * Tq
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61 | Tpha2 = (PHSEG2+1) * Tq
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62 | Choosing 'PHSEG1' = 3 yields Tpha1 = 4 us and choosing
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63 | 'PHSEG2' = 2 yields Tpha2 = 3 us.
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64 |
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65 | Summarizing:
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66 | Tq = 1 us
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67 | Tbit = Tsync + Tprop + Tpha1 + Tpha2
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68 | = ( 1 + 2 + 4 + 3 ) * Tq = 10 us
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69 | ^
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70 | sampling point
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71 | */
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72 | can_write_register(CNF1,
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73 | _BV(SJW0) |
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74 | _BV(BRP1) | _BV(BRP0) /* 'BRP' = 3 */
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75 | );
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76 | can_write_register(CNF2,
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77 | _BV(SAM) |
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78 | _BV(BTLMODE) |
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79 | _BV(PHSEG11) | _BV(PHSEG10) | /* 'PHSEG1' = 3 */
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80 | _BV(PRSEG0) /* 'PRSEG' = 1 */
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81 | );
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82 | can_write_register(CNF3,
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83 | _BV(PHSEG21) /* 'PHSEG2' = 2 */
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84 | );
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85 |
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86 |
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87 |
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88 | /* Interrupts on reception into any of the two RX buffers and on
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89 | completing transmission of any of the three TX buffers. */
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90 | can_write_register(CANINTE,
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91 | _BV(RX1IE) | _BV(RX0IE) |
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92 | _BV(TX2IE) | _BV(TX1IE) | _BV(TX0IE)
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93 | );
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94 |
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95 |
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96 | /* Accept anything in first buffer */
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97 | can_write_register(RXB0CTRL, _BV(RXM1) | _BV(RXM0));
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98 |
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99 |
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100 |
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101 | /* Leave configuration mode and speed up clock output. */
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102 | can_write_register(CANCTRL, _BV(CLKEN));
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103 | }
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