1 | library ieee;
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2 | use ieee.std_logic_1164.all;
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3 | use ieee.std_logic_arith.all;
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4 | use ieee.std_logic_unsigned.all;
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5 | use ieee.numeric_std.all;
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6 |
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7 | entity vga_control is
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8 | port (
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9 | reset, taster : in std_logic;
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10 | clk : in std_logic;
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11 |
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12 | VGA_CLK, -- Should be 25.125 MHz VGA_CLK, Dot clock to DAC
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13 | VGA_HS, -- Active Low Horizontal Sync
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14 | VGA_VS, -- Active Low Vertical Sync
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15 | VGA_BLANK, -- Active Low DAC blanking control
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16 | VGA_SYNC : out std_logic; -- Active Low DAC Sync on Green
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17 | VGA_R, VGA_G, VGA_B : out std_logic_vector(7 downto 0);
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18 | ledtest1, ledtest2, ledtest3 : out std_logic := '0'
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19 | );
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20 |
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21 | end vga_control;
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22 |
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23 | architecture rtl of vga_control is
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24 |
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25 | -- Video parameters
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26 |
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27 | constant HTOTAL : integer := 800;
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28 | constant HSYNC : integer := 96;
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29 | constant HBACK_PORCH : integer := 48;
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30 | constant HACTIVE : integer := 640;
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31 | constant HFRONT_PORCH : integer := 16;
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32 | constant VTOTAL : integer := 525;
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33 | constant VSYNC : integer := 2;
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34 | constant VBACK_PORCH : integer := 33;
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35 | constant VACTIVE : integer := 480;
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36 | constant VFRONT_PORCH : integer := 10;
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37 | constant RECTANGLE_HSTART : integer := 100;
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38 | constant RECTANGLE_HEND : integer := 540;
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39 | constant RECTANGLE_VSTART : integer := 100;
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40 | constant RECTANGLE_VEND : integer := 380;
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41 |
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42 | signal Hcount : std_logic_vector(9 downto 0):= "0000000000"; -- Horizontal position (0 - 800)
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43 | signal Vcount : std_logic_vector(9 downto 0):= "0000000000"; -- Vertical position (0 - 524)
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44 | signal EndOfLine, EndOfField : std_logic :='0';
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45 | signal vga_hblank, vga_hsync,
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46 | vga_vblank, vga_vsync : std_logic; -- Sync. signals
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47 |
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48 | signal rectangle_h, rectangle_v, rectangle : std_logic; -- rectangle area
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49 |
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50 | begin
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51 |
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52 | test : process (clk)
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53 | begin
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54 |
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55 | if taster= '1' then
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56 | ledtest1<='0';
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57 | else
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58 | ledtest1<='1';
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59 | end if;
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60 |
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61 | end process test;
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62 |
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63 |
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64 |
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65 | HCounter : process (clk)
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66 | begin
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67 |
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68 | if reset = '0' then
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69 | Hcount <= (others=> '0');
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70 | ledtest2<='1';
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71 | elsif (clk'event and clk = '1') then
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72 | ledtest2<='0';
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73 | if EndOfLine = '1' then
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74 | Hcount <= (others=> '0');
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75 | else
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76 | Hcount <= Hcount + 1;
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77 |
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78 | end if;
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79 | end if;
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80 |
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81 | end process;
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82 |
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83 |
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84 | VCounter: process (clk)
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85 | begin
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86 |
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87 | if reset = '0' then
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88 | Vcount <= (others=> '0');
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89 |
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90 | elsif (clk'event and clk = '1') then
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91 | if EndOfLine = '1' then
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92 | if EndOfField = '1' then
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93 | Vcount <= (others=> '0');
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94 |
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95 | else
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96 | Vcount <= Vcount + 1;
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97 | end if;
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98 | end if;
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99 | end if;
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100 | end process VCounter;
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101 |
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102 |
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103 | HSyncGen : process (clk)
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104 | begin
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105 | if reset = '1' then
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106 | vga_hsync <= '1';
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107 | elsif clk'event and clk = '1' then
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108 | if EndOfLine = '1' then
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109 | vga_hsync <= '1';
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110 | elsif Hcount = HSYNC - 1 then
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111 | vga_hsync <= '0';
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112 | end if;
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113 | end if;
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114 | end process HSyncGen;
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115 |
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116 | HBlankGen : process (clk)
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117 | begin
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118 |
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119 | if reset='1' then
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120 | vga_hblank <= '1';
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121 |
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122 | elsif clk'event and clk='1' then
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123 |
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124 | if Hcount = HSYNC + HBACK_PORCH then
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125 | vga_hblank <= '0';
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126 | elsif Hcount = HSYNC + HBACK_PORCH + HACTIVE then
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127 | vga_hblank <= '1';
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128 | end if;
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129 |
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130 | end if;
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131 | end process HBlankGen;
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132 |
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133 |
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134 |
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135 | VSyncGen : process (clk)
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136 | begin
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137 |
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138 | if reset='1' then
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139 | vga_vsync <= '1';
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140 | elsif clk'event and clk = '1' then
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141 | if EndOfLine ='1' then
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142 | if EndOfField = '1' then
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143 | vga_vsync <= '1';
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144 | elsif Vcount = VSYNC - 1 then
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145 | vga_vsync <= '0';
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146 | end if;
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147 | end if;
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148 | end if;
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149 | end process VSyncGen;
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150 |
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151 |
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152 | VBlankGen : process (clk)
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153 | begin
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154 |
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155 | if reset = '1' then
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156 | vga_vblank <= '1';
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157 | elsif clk'event and clk = '1' then
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158 | if EndOfLine = '1' then
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159 | if Vcount = VSYNC + VBACK_PORCH - 1 then
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160 | vga_vblank <= '0';
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161 | elsif Vcount = VSYNC + VBACK_PORCH + VACTIVE - 1 then
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162 | vga_vblank <= '1';
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163 | end if;
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164 | end if;
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165 | end if;
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166 | end process VBlankGen;
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167 |
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168 |
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169 | RectangleHGen : process (clk)
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170 | begin
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171 |
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172 | if reset = '1' then
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173 | rectangle_h <= '1';
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174 | elsif clk'event and clk = '1' then
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175 | if Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HSTART then
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176 | rectangle_h <= '1';
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177 | elsif Hcount = HSYNC + HBACK_PORCH + RECTANGLE_HEND then
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178 | rectangle_h <= '0';
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179 | end if;
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180 | end if;
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181 | end process RectangleHGen;
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182 |
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183 |
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184 | RectangleVGen : process (clk)
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185 | begin
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186 | if reset = '1' then
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187 | rectangle_v <= '0';
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188 | elsif clk'event and clk = '1' then
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189 | if EndOfLine = '1' then
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190 | if Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VSTART then
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191 | rectangle_v <= '1';
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192 | elsif Vcount = VSYNC + VBACK_PORCH - 1 + RECTANGLE_VEND then
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193 | rectangle_v <= '0';
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194 |
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195 | end if;
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196 | end if;
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197 | end if;
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198 | end process RectangleVGen;
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199 |
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200 | rectangle <= rectangle_h and rectangle_v;
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201 |
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202 |
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203 |
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204 | VideoOut: process (clk)
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205 | begin
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206 |
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207 | if reset = '1' then
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208 | VGA_R <= "00000000";
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209 | VGA_G <= "00000000";
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210 | VGA_B <= "00000000";
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211 | elsif clk'event and clk = '1' then
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212 |
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213 | if rectangle = '1' then
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214 | VGA_R <= "11111111";
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215 | VGA_G <= "11111111";
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216 | VGA_B <= "11111111";
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217 | elsif vga_hblank = '0' and vga_vblank ='0' then
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218 | VGA_R <= "00000000";
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219 | VGA_G <= "00000000";
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220 | VGA_B <= "11111111";
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221 | else
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222 | VGA_R <= "00000000";
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223 | VGA_G <= "00000000";
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224 | VGA_B <= "00000000";
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225 | end if;
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226 | end if;
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227 | end process VideoOut;
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228 |
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229 |
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230 | vga_clk_gen : PROCESS(clk)--devides 50MHz clock in 2, making it a 25MHz clock
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231 | VARIABLE count : INTEGER := 0;
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232 | BEGIN
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233 |
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234 | IF rising_edge(clk) THEN
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235 | IF count = 0 THEN
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236 | VGA_CLK <= '1'; --1 period of 50MHz high
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237 | count := 1;
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238 | ELSIF count = 1 THEN
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239 | VGA_CLK <= '0';
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240 | count := 0;
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241 | END IF;
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242 | END IF;
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243 | END PROCESS vga_clk_gen;
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244 |
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245 |
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246 |
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247 | VGA_HS <= not vga_hsync;
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248 | VGA_VS <= not vga_vsync;
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249 | VGA_SYNC <='0';
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250 | VGA_BLANK <= not (vga_hsync or vga_vsync);
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251 |
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252 | end rtl;
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