1 | library IEEE;
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2 | use IEEE.STD_LOGIC_1164.ALL;
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3 | use IEEE.NUMERIC_STD.ALL;
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4 |
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5 | -- Uncomment the following library declaration if using
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6 | -- arithmetic functions with Signed or Unsigned values
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7 | --use IEEE.NUMERIC_STD.ALL;
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8 |
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9 | -- Uncomment the following library declaration if instantiating
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10 | -- any Xilinx primitives in this code.
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11 | --library UNISIM;
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12 | --use UNISIM.VComponents.all;
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13 |
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14 | entity test_max is
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15 | Port ( max_in : in STD_LOGIC_VECTOR (11 downto 0);
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16 | -- max_out : out STD_LOGIC_VECTOR (11 downto 0);
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17 | -- bcd_4_out : out STD_LOGIC_VECTOR( 3 downto 0);
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18 | anod : out std_logic_vector(3 downto 0);
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19 | a2g : out std_logic_vector(6 downto 0);
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20 | clk : in STD_LOGIC);
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21 | end test_max;
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22 |
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23 | architecture Behavioral of test_max is
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24 |
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25 |
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26 | component Vector2BCD
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27 | Port ( clk : in std_logic;
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28 | vector : in std_logic_vector (11 downto 0);
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29 | start : in std_logic;
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30 | busy : out std_logic;
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31 | overflow : out std_logic;
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32 | bcd : out std_logic_vector (15 downto 0));
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33 | end component;
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34 |
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35 |
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36 |
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37 | --component hex7seg
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38 | --Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
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39 | -- a_to_g : out STD_LOGIC_VECTOR (6 downto 0));
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40 | --end component;
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41 |
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42 |
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43 |
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44 | component multiplexer
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45 | Port ( clk : in STD_LOGIC;
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46 | seg1 : in STD_LOGIC_VECTOR (6 downto 0);
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47 | seg2 : in STD_LOGIC_VECTOR (6 downto 0);
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48 | seg3 : in STD_LOGIC_VECTOR (6 downto 0);
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49 | seg4 : in STD_LOGIC_VECTOR (6 downto 0);
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50 | seg_out : out STD_LOGIC_VECTOR(6 downto 0);
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51 | an : out STD_LOGIC_VECTOR(3 downto 0));
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52 | end component;
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53 |
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54 |
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55 | ------------ SIGNALE ------------------------
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56 |
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57 | signal busy : STD_LOGIC;
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58 | signal bcd : std_logic_vector(15 downto 0);
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59 |
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60 | signal sel : STD_LOGIC_VECTOR (1 downto 0);
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61 | --signal x_bcd : STD_LOGIC_VECTOR (3 downto 0);
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62 | signal counter : natural range 999999 downto 0;
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63 |
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64 | signal clk2 : std_logic;
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65 |
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66 |
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67 |
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68 | signal segm1 : STD_LOGIC_VECTOR(3 downto 0);
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69 | signal segm2 : STD_LOGIC_VECTOR(3 downto 0);
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70 | signal segm3 : STD_LOGIC_VECTOR(3 downto 0);
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71 | signal segm4 : STD_LOGIC_VECTOR(3 downto 0);
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72 |
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73 | signal a_to_g1 : STD_LOGIC_VECTOR(6 downto 0);
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74 | signal a_to_g2 : STD_LOGIC_VECTOR(6 downto 0);
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75 | signal a_to_g3 : STD_LOGIC_VECTOR(6 downto 0);
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76 | signal a_to_g4 : STD_LOGIC_VECTOR(6 downto 0);
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77 |
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78 | ----------------------------------------------
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79 |
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80 |
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81 | begin
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82 |
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83 | ---------------- SCHRITT 1 ---------------
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84 |
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85 | Comp_BCD : Vector2BCD port map ( clk => clk,
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86 | vector => max_in,
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87 | start => '1',
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88 | busy => busy,
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89 | overflow => open,
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90 | bcd => bcd);
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91 | --------------------------------------------
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92 |
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93 | --SEG : hex7seg port map ( x => x_bcd,
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94 | -- a_to_g => a2g
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95 | -- );
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96 | --
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97 | --
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98 | --
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99 |
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100 | COMP_Multiplexer : multiplexer port map ( clk => clk2,
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101 | seg1 => a_to_g1 ,
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102 | seg2 => a_to_g2,
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103 | seg3 => a_to_g3 ,
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104 | seg4 => a_to_g4,
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105 | seg_out => a2g,
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106 | an => anod);
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107 |
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108 |
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109 |
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110 | ------- SCHRITT 2 ----------
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111 |
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112 | segm1 <= bcd(15 downto 12);
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113 | segm2 <= bcd(11 downto 8);
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114 | segm3 <= bcd(7 downto 4);
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115 | segm4 <= bcd(3 downto 0);
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116 |
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117 | ------------------------------
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118 |
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119 |
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120 |
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121 | ----- 50 HZ Generator ------
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122 |
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123 | process(clk)
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124 | begin
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125 | if (counter = 999999) then
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126 | counter <= 0;
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127 | else
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128 | counter <= counter + 1;
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129 | end if;
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130 |
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131 | if counter < 500000 then
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132 | clk2 <= '1';
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133 | else
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134 | clk2 <= '0';
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135 | end if;
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136 | end process;
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137 |
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138 |
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139 |
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140 |
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141 |
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142 |
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143 | process (segm1)
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144 | begin
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145 | case segm1 is
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146 | when X"0" => a_to_g1 <= "0000001"; --0
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147 | when X"1" => a_to_g1 <= "1001111"; --1
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148 | when X"2" => a_to_g1 <= "0010010"; --2
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149 | when X"3" => a_to_g1 <= "0000110"; --3
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150 | when X"4" => a_to_g1 <= "1001100"; --4
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151 | when X"5" => a_to_g1 <= "0100100"; --5
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152 | when X"6" => a_to_g1 <= "0100000"; --6
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153 | when X"7" => a_to_g1 <= "0001101"; --7
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154 | when X"8" => a_to_g1 <= "0000000"; --8
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155 | when X"9" => a_to_g1 <= "0000100"; --9
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156 | when X"A" => a_to_g1 <= "0001000"; --A
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157 | when X"B" => a_to_g1 <= "1100000"; --b
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158 | when X"C" => a_to_g1 <= "0110001"; --C
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159 | when X"D" => a_to_g1 <= "1000010"; --d
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160 | when X"E" => a_to_g1 <= "0110000"; --E
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161 | when others => a_to_g1 <= "0111000"; --F
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162 | end case;
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163 | end process;
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164 |
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165 |
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166 |
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167 |
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168 | process (segm2)
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169 | begin
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170 | case segm2 is
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171 | when X"0" => a_to_g2 <= "0000001"; --0
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172 | when X"1" => a_to_g2 <= "1001111"; --1
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173 | when X"2" => a_to_g2 <= "0010010"; --2
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174 | when X"3" => a_to_g2 <= "0000110"; --3
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175 | when X"4" => a_to_g2 <= "1001100"; --4
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176 | when X"5" => a_to_g2 <= "0100100"; --5
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177 | when X"6" => a_to_g2 <= "0100000"; --6
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178 | when X"7" => a_to_g2 <= "0001101"; --7
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179 | when X"8" => a_to_g2 <= "0000000"; --8
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180 | when X"9" => a_to_g2 <= "0000100"; --9
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181 | when X"A" => a_to_g2 <= "0001000"; --A
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182 | when X"B" => a_to_g2 <= "1100000"; --b
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183 | when X"C" => a_to_g2 <= "0110001"; --C
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184 | when X"D" => a_to_g2 <= "1000010"; --d
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185 | when X"E" => a_to_g2 <= "0110000"; --E
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186 | when others => a_to_g2 <= "0111000"; --F
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187 | end case;
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188 | end process;
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189 |
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190 |
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191 |
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192 | process (segm3)
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193 | begin
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194 | case segm3 is
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195 | when X"0" => a_to_g3 <= "0000001"; --0
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196 | when X"1" => a_to_g3 <= "1001111"; --1
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197 | when X"2" => a_to_g3 <= "0010010"; --2
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198 | when X"3" => a_to_g3 <= "0000110"; --3
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199 | when X"4" => a_to_g3 <= "1001100"; --4
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200 | when X"5" => a_to_g3 <= "0100100"; --5
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201 | when X"6" => a_to_g3 <= "0100000"; --6
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202 | when X"7" => a_to_g3 <= "0001101"; --7
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203 | when X"8" => a_to_g3 <= "0000000"; --8
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204 | when X"9" => a_to_g3 <= "0000100"; --9
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205 | when X"A" => a_to_g3 <= "0001000"; --A
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206 | when X"B" => a_to_g3 <= "1100000"; --b
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207 | when X"C" => a_to_g3 <= "0110001"; --C
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208 | when X"D" => a_to_g3 <= "1000010"; --d
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209 | when X"E" => a_to_g3 <= "0110000"; --E
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210 | when others => a_to_g3 <= "0111000"; --F
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211 | end case;
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212 | end process;
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213 |
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214 |
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215 | process (segm4)
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216 | begin
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217 | case segm4 is
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218 | when X"0" => a_to_g4 <= "0000001"; --0
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219 | when X"1" => a_to_g4 <= "1001111"; --1
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220 | when X"2" => a_to_g4 <= "0010010"; --2
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221 | when X"3" => a_to_g4 <= "0000110"; --3
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222 | when X"4" => a_to_g4 <= "1001100"; --4
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223 | when X"5" => a_to_g4 <= "0100100"; --5
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224 | when X"6" => a_to_g4 <= "0100000"; --6
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225 | when X"7" => a_to_g4 <= "0001101"; --7
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226 | when X"8" => a_to_g4 <= "0000000"; --8
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227 | when X"9" => a_to_g4 <= "0000100"; --9
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228 | when X"A" => a_to_g4 <= "0001000"; --A
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229 | when X"B" => a_to_g4 <= "1100000"; --b
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230 | when X"C" => a_to_g4 <= "0110001"; --C
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231 | when X"D" => a_to_g4 <= "1000010"; --d
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232 | when X"E" => a_to_g4<= "0110000"; --E
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233 | when others => a_to_g4 <= "0111000"; --F
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234 | end case;
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235 | end process;
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236 |
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237 |
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238 |
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239 |
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240 |
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241 |
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242 |
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243 | end Behavioral;
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